Specifications

CM-X300 CoM
44 CM-X300 Reference Guide Rev 1.31 30-Dec-2010
 Use the following equation to calculate the cycle time of the scaled counter clock:
Scaled counter clock cycle time = 76.9 ns x (PWMCRx[PRESCALE] + 1)
Both the period and the duty cycle of the PWM are based on the scaled counter clock cycle
time. The PWMx_OUT signal is asserted for the number of scaled counter clock cycles
equal to PWMDCRx[DCYCLE].
 To calculate the duty cycle time of the PWM,use the following equation:
Duty cycle time = Scaled counter clock cycle time x PWMDCRx[DCYCLE]
 which also equals:
Duty cycle time = 76.9nS x (PWMCRx[PRESCALE] + 1) x PWMDCRx[DCYCLE]
The PWM Period Control register (PWMPCRx) determines the number of scaled counter
clock cycles each PWM period contains. The actual number of clocks is the value of
PWMPCRx[PV] plus one. When the RST comparator equals (PWMPCRx[PV]+1), the
comparators and the flip-flop are reset, and the values of the PWMDCR_HOLDx,
PWMCR_HOLDx, and PWMPCR_HOLDx registers are loaded from the control block.
 Use the following equation to calculate the period of the PWM:
PWM period = Scaled Counter Clock period x (PWMPCRx[PV] + 1)
 which also equals:
PWM cycle time = 76.9nS x (PWMCRx[PRESCALE]+1) x (PWMPCRx[PV] + 1)
 Calculate values based on the necessary PWM cycle time and duty cycle with the
following equations:
Choose a PWMCRx[PRESCALE] value that is appropriate for all your PWM
outputs.
PWMPCRx[PV] = PWM cycle time / (76.0nS X (PWMCRx[PRESCALE] + 1)) – 1
Duty cycle time = PWM cycle time * Duty Cycle%
PWMDCRx[DCYCLE] = Duty cycle time / (76.0nS X (PWMCRx[PRESCALE] + 1
))
For example, to create a 60% duty cycle 500 kHz signal, set PWMCRx[PRESCALE] to 0,
PWMPCRx[PV] to 26 (0x1A), and PWMDCRx[DCYCLE] to 16 (0x10).
Note: To produce a toggle of the signal, the value of the PWMPCRx[PV]must be equal to
or greater than PWMDCRx[DCYCLE]. If PWMPCRx[PV] is less than
PWMDCRx[DCYCLE], the PWMx_OUT signal remains high. If PWMDCRx[DCYCLE]
equals zero, the signal remains low.
The PWMDCRx[FD] bit determines if PWMx_OUT is always asserted. When this bit is
set, PWMx_OUT remains high until PWMDCRx[FD] is cleared.
3.3.19.5 PWM Register Summary
The PWM contains three registers that control the clock, the period, and the duty cycle
timing of the PWMx_OUT.
Table 46 PWM Registers
Address
Description
0x40C0_0000
PWM 1 Control Register (PWMCR1)
0x40C0_0004
PWM 1 Duty Cycle Register (PWMDCR1)
0x40C0_0008
PWM 1 Period Control Register (PWMPCR1)
0x40B0_0010
PWM 2 Control Register (PWMCR2)
0x40B0_0014
PWM 2 Duty Cycle Register (PWMDCR2)
0x40B0_0018
PWM 2 Period Control Register (PWMPCR2)