Specifications
Functional Description
30-Dec-2010 CM-X300 Reference Guide Rev 1.31 43
For PWMPCRx[PV] values 0x005 and larger—After a register value is altered, the
PWM_OUTx signal changes when the previously programmed waveform cycle is
complete.
For PWMPCRx[PV] values less than 0x005—After a register value is altered, the
PWM_OUTx signal changes after two waveform cycles
Figure 9 Effect of PWMCR2 Settings
Programming PWMCRx[PRESCALE] configures the prescaled counter clock. Two timing
examples are provided in Figure 9. Both examples have the PWMDCRx and PWMPCRx
registers set with the same 50% duty cycle setting. The first example shows the effect on
the scaled counter clock effectively being divided by two with a setting of 0x01, while the
second example shows the scaled counter clock being divided by four with a setting of
0x03. See Section 3.3.19.4 for more information regarding the calculation of waveform
values.
3.3.19.3 PWM Reset Sequence
During system reset, the PWMCRx and PWMDCRx registers are reset to 0x0 and the
PWMPCRx register is set to 0x004. Reset places the PWMx_OUT channel in a steady low
state. The PWMx_OUT channel remains reset to 0x0 until the PWMDCRx register is
programed with a non-zero value. Therefore,system reset results in no pulse-width
modulated signal.
3.3.19.4 Programming Considerations
The PWM uses three registers to configure the output of the PWMx signal: PWMCRx,
PWMDCRx, and PWMPCRx.
PWM timing is based on the input clock to the PWMx controller, PSCLK_PWMx, which is
fixed at 13 MHz. This signal is divided by (PWMCRx[PRESCALE] + 1) to generate the
scaled counter clock. The 6-bit PRESCALE field allows the input clock to be divided by
values between 1 (PRESCALE = 0) and 64 (PRESCALE = 63). The scaled counter clock is
further divided by contents of the PWMDCRx and PWMPCRx registers to generate the
duty cycle and period of the PWMx signal.
Use the following equation to calculate the frequency of the scaled counter clock:
Scaled counter clock frequency = 13 MHz / (PWMCRx[PRESCALE] + 1)