Specifications

CM-X300 CoM
36 CM-X300 Reference Guide Rev 1.31 30-Dec-2010
Name
Address
Description
GPCR2
0x40E0_002C
GPIO Pin Output Clear Register 2. An output port is cleared when a 1 is
written to the corresponding bit within the GPCR2 (write-only register;
reads return unpredictable values).
0 = Port level unaffected.
1 = If the port is configured as an output, clear the port level logic low.
GRER2
0x40E0_0038
GPIO Rising-Edge Detect-Enable Register 2. GRER2 bit is set to cause a
GEDR2 status bit to be set when the port transitions from Logic Level low
to Logic Level high.
0 = Disable rising-edge detect enable.
1 = Set the corresponding GEDR status bit when a rising edge is detected
on the GPIO port.
GFER2
0x40E0_0044
GPIO Falling-Edge Detect-Enable Register 2. GFER2 bit is set to cause a
GEDR2 status bit to be set when the port transitions from Logic Level high
to Logic Level low.
0 = No falling-edge detect enable.
1 = Set the corresponding GEDR status bit when a falling edge is detected
on the GPIO port.
GEDR2
0x40E0_0050
GPIO Edge Detect Status Register 2 . When an edge-detect occurs on a
port that matches the type of edge programmed in the GRER2 and/or
GFER2 registers, the corresponding status bit is set in GEDR2. When a
GEDR2 bit is set, the CPU must clear it. GEDR2 status bits are cleared by
writing a 1 to them. Writing a 0 has no effect. Each edge-detect that sets
the corresponding GEDR2 status bit for GPIO pins can trigger an interrupt
request.
0 = No edge detect on the port as specified in GRER2 and/or GFER2.
1 = Edge detect on the port as specified in GRER2 and/or GFER2.
GSDR2
0x40E0_0408
GPIO Pin Bit-Wise Set Direction Register 2 . If a direction bit is set, the
corresponding bit in GPDR2 is set and the GPIO function is configured as
an output. If it is cleared, no change in the GPIO functionality or the
GPDR2 register occurs.
0 = GPDR2 bit not affected.
1 = GPDR2 bit is set and GPIO function is set to OUTPUT.
GCDR2
0x40E0_0428
GPIO Pin Bit-Wise Clear Direction Register 2 . If a direction bit is set, the
corresponding bit in GPDR2 is cleared and the GPIO function is
configured as an input. If it is cleared, no change in the GPIO functionality
or the GPDR2 register occurs.
0 = GPDR2 bit is not affected.
1 = GPDR2 bit is cleared and a GPIO function is set to INPUT.
GSRER2
0x40E0_0448
GPIO Bit-Wise Set Rising-Edge Register 2. If a bit is set, the
corresponding bit in GRER2 is set and the GPIO function is configured to
cause a GEDR2 status bit to be set when the port transitions from Logic
Level zero (0) to Logic Level one (1). If the bit is cleared, no change in the
GPIO functionality or GRERx occurs
0 = GRER2 bit not affected.
1 = GRER2 bit is set.
GCRER2
0x40E0_0468
GPIO Bit-wise Clear Rising-Edge Detect-Enable Register 2. If a bit is set,
the corresponding bit in GRER2 is cleared and the GPIO function is
configured to not cause a GEDR2 status bit to be set when the port
transitions from Logic Level zero (0) to Logic Level one (1). If the bit is
cleared, no change in the GPIO functionality or the GRER2 register occurs
0 = GRER2 bit not affected.
1 = GRER2 bit is cleared
GSFER2
0x40E0_0488
GPIO Bit-Wise Set Falling-Edge Register 2. If a bit is set, the
corresponding bit in GFER2 is set and the GPIO function is configured to
cause a GEDR2 status bit to be set when the port transitions from logic-
level one (1) to logic-level zero (0). If the bit is cleared, no change in the
GPIO functionality or the GFER2 register occurs
0 = GFER2 bit not affected
1 = GFER2 bit is set
GCFER2
0x40E0_04A8
GPIO Bit-wise Clear Falling-Edge Detect-Enable Register 2. If a bit is set,
the corresponding bit in GFER2 is cleared and the GPIO function is
configured to not cause a GEDR2 status bit to be set when the port
transitions from logic-level one (1) to logic-level zero (0) If the bit is
cleared, no change occurs in the GPIO functionality or the GFER2 register.
0 = GFER2 bit not affected
1 = GFER2 bit is cleared