Specifications

Functional Description
30-Dec-2010 CM-X300 Reference Guide Rev 1.31 35
When programmed as an input, a GPIO port can also serve as an interrupt source. At the
assertion of all resets, all ports are configured as inputs and remain inputs until they are
configured either by the boot process or by user software.
The direction of the GPIO ports is controlled by writing to the CPU‘s GPIO Pin Direction
register (GPDR2). When the GPIO pin is programmed as an output, the port is set by
writing to the GPIO Pin Output Set Register (GPSR2) and cleared by writing to the GPIO
Pin Output Clear Register (GPCR2). The Set and Clear registers can be written regardless
of whether the port is configured as an input or an output. The programmed output state
takes effect when the port is reconfigured as an output.
When the GPIO pin is programmed as an input, it can be configured to detect a rising edge,
falling edge, or both through the GPIO Rising-Edge Detect Enable Register (GRER2) and
the GPIO Falling-Edge Detect Enable Register (GFER2). The state of the edge-detect can
be read through the GPIO Edge Detect Status Register (GEDR2). These edge-detects can
be programmed to generate interrupts.
The value of each GPIO port is read through the GPIO Pin-Level Register (GPLR2). This
register can be read at any time and can confirm the port state for both input and output
configurations.
Note: GPIO18 is used internally by the u-boot when booting the module. It should not be
pulled-up or down by values lower than 100K on the baseboard.
Table 32 CPU GPIO Signals
CM-X300 Signal
Name
Type
Description
GPIO[90:80]
I/O
Dedicated GPIO (GPIO80..82 are available in C624 modules only. In the
C624M modules using these GPIO lines will interfere with USB host
function)
GPIO[52:39]
I/O
Camera interface GPIO (shared with CIF pins). These GPIO‘s are
available for GPIO use only in C624M modules. These signals are routed
to CAMI in C624 modules, too, but cannot be used as GPIO as they serve
as UTMI USB transmitter‘s interface onboard.
GPIO[37:30]
I/O
FFUART GPIO (shared with FFUART pins). Available only in C624
modules. These pins are used for ULPI transmitter interface in C624M
modules and are not available on CAMI.
GPIO[125:115]
I/O
Keypad GPIO (shared with keypad pins)
GPIO[114:111]
I/O
BTUART GPIO (shared with BTUART function pins)
GPIO[88:85]
I/O
SSP1 GPIO (shared with SSP1 pins)
Each of the 32-bit registers described maps its bits [31:0] to the GPIO pins [95:64].
Software should not modify any bits except [26:16] mapped accordingly to the CPU GPIO
signals [90:80] available on the CAMI.
Table 33 CPU GPIO Registers
Name
Address
Description
GPLR2
0x40E0_0008
GPIO Pin-Level Register 2. Shows the current value of a particular port
(regardless of the programmed port direction):
0 = Port state is low
1 = Port state is high
GPDR2
2x40E0_0014
GPIO Pin Direction Register 2. If a direction bit is set, the GPIO pin is an
output. If it is cleared, it is an input. A pair of set/clear registers (GSDR2
and GCDR2) is also provided to enable the setting and clearing of
individual bits of the GPDR2 register.
0 = Port configured as an input
1 = Port configured as an output
GPSR2
0x40E0_0020
GPIO Pin Output Set Register 2. An output port is set by writing a 1 to its
corresponding bit in the GPSR2 (write-only register; reads return
unpredictable values).
0 = Port level unaffected.
1 = If the port is configured as an output, set the port level logic high