Specifications

Functional Description
30-Dec-2010 CM-X300 Reference Guide Rev 1.31 29
Table 22 LCD Signals
CM-X300 Signal
Name
Type
Description
LCD-R[5:1]
O
Red channel data for TFT panels. Bit 0 of the panel‘s red channel should
be connected to GND.
LCD-G[5:0]
O
Green channel data for TFT panels.
LCD-B[5:1]
O
Blue channel data for TFT panels. Bit 0 of the panel‘s blue channel should
be connected to GND.
LCD-LP
O
HSYNC for TFT panels.
LCD-FRM
O
VSYNC for TFT panels.
LCD-SCK
O
Pixel clock.
LCD-DE
O
3.3.8.1 Limitations of Display Controller Capabilities
The LCD controller provides a variety of programmable options including display type,
resolution, frame buffer, pixel depth, overlays, hardware cursor, and output data formatting.
Although all programmable combinations are possible, the available selection of displays
dictates which combinations of these programmable options are practical. The type of
external memory system used limits the bandwidth of the LCD DMA controller, which, in
turn, limits the resolution and type of screen that can be controlled. Use information below
to determine the maximum bandwidth of the internal bus that the LCD can use without
negatively affecting all other functions.
The equations in this section provide a way to estimate the LCD bandwidth needed to drive
an LCD panel with the PXA3xx processor. LCD bandwidth can affect overall system
performance by reducing the available system memory bus bandwidth. The CM-X300‘s
memory bus clock frequency is 130 MHz, data rate 260 MT/s. The LCD controller shares
the System Bus #1 with other devices (see Figure 6 below)
Figure 6 PXA300 Processor Block Diagram
The LCD controller can be programmed with timing values that control the refresh rate and
the needed LCD bandwidth for a specific LCD panel. The total needed memory bus
bandwidth can be defined as the LCD bandwidth plus the system memory bus bandwidth
used by any other running processes in the processor. When the total memory bus