Specifications

CM-X300 CoM
26 CM-X300 Reference Guide Rev 1.31 30-Dec-2010
COM-A-TX#
O
Serial Data Out: transmits the serial data from the internal serial port
controller to the external serial device or DCE.
3.3.5.3 Partial-Function UART
This is the CPU‘s UART2. The interface is routed to the CAMI COM-D serial port and
uses TTL-levels signaling. The port‘s pin descriptions are listed in Table 17.
Table 17 Partial-Function UART Signals
CM-X300 Signal
Name
Type
Description
COM-D-RX
I
Serial Data In: receives the serial data from the external serial device or
DCE into the internal serial port controller.
COM-D-TX
O
Serial Data Out: transmits the serial data from the internal serial port
controller to the external serial device or DCE.
COM-D-CTS#
I
Clear To Send: is sent back to the serial port to indicate that the external
data carrier equipment (DCE) is ready to accept data.
COM-D-RTS#
O
Request To Send: indicates to the external DCE that the internal serial port
controller is ready to send data.
3.3.6 Local Bus
The CM-X300‘s local bus is the unbuffered CPU‘s Data Flash Interface (DFI). The DFI is
shared between the NAND Flash Controller (NFC) and Static Memory Controller (SMC).
The NAND Flash Controller (NFC) supports large- and small-block, 8-bit and 16-bit
NAND flash devices.
The Static Memory Controller (SMC) maintains multiple static-memory types, such as
synchronous and asynchronous flash devices, SRAM and SRAM-like variable-latency IO
devices (VLIO).
3.3.6.1 Local Bus Signal Description
The Static Memory Controller (SMC) signals are listed in Table 18. The NAND Flash
Controller (NFC) signals are listed in Table 19.
Note that some signals are shared between the two controllers.
Table 18 Local Bus Signals (SMC)
CM-X300 Signal
Name
Type
Description
DF-IO[15:0]
I/O
Bidirectional data/address bus
DF_CLE_nOE
O
Output enable
DF_ALE_nWE
O
Write enable
LB-CS[3:0]#
nXCVREN
O
Chip selects.
LB-CS3 may be configured as nXCVREN (External transceiver enable)
signal. It is asserted along with the Output Enable (DF_CLE_nOE) during
read accesses and one DF_SLCK cycle before the Write Enable
(DF_ALE_nWE) during write accesses.
0 = Enable transceiver
1 = Disable transceiver
LB-LUA#
O
Latch upper address. Used to latch the high-order address bits during the
upper address cycle.
LB-LLA#
O
Latch lower address. Used to latch the low-order address bits during the
lower address cycle.
DF-A[3:0]
O
Low-order address bits. Used as the lowest four address bits during an
asynchronous burst transfer of the values in the lower address cycle on the
DF-IO[15:0]