CM-X300 CoM Reference Guide Rev 1.
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Table of Contents Table of Contents 1 INTRODUCTION ................................................................................................. 9 1.1 1.2 1.3 1.4 2 OVERVIEW ........................................................................................................ 10 2.1 2.2 3 About This Document ........................................................................................ 9 CM-X300 Part Number Legend ........................................................................
CM-X300 CoM 3.3.9.2 USB Interfaces Routing ..................................................................... 32 3.3.9.3 USB1 Interface ................................................................................... 32 3.3.9.4 USB2 Interface ................................................................................... 32 3.3.9.5 USB3 Interface ................................................................................... 32 3.3.10 MMC/SD/SDIO Controller ...................................
Table of Contents List of Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 30-Dec-2010 CM-X300 Block Diagram............................................................................ 10 CM-X300 Top View Diagram ..................................................................... 13 CM-X300 Bottom View Diagram ............................................................... 14 Magnetic Interconnect Schematic ....................................
CM-X300 CoM List of Tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Table 30 Table 31 Table 32 Table 33 Table 34 Table 35 Table 36 Table 37 Table 38 Table 39 Table 40 Table 41 Table 42 6 Acronyms .......................................................................................................
List of Tables Table 43 Table 44 Table 45 Table 46 Table 47 Table 48 Table 49 Table 50 Table 51 Table 52 Table 53 Table 54 30-Dec-2010 SSP1 Port Signals ........................................................................................ 40 SSP3 Port Signals ........................................................................................ 40 PWM Signals ............................................................................................... 41 PWM Registers .............................
CM-X300 CoM Revision Information Date Description September 01, 2008 October 29, 2008 November 30, 2008 December 01, 2008 December 14, 2008 March 17, 2009 Preliminary release CM-X300 rev 1.1 release Added section 3.3.19, PWM Controller. Added section 3.3.8.1, Limitations of Display Controller Capabilities. Added section 3.3.4.2, Implementing Magnetics CM-X300 Revision 1.2 introduced Block Diagram (Figure 1) updated Section 2.2 CM-X300 Features updated Section 3.3.8.
Introduction 1 INTRODUCTION 1.1 About This Document This document is part of a set of reference documents providing information necessary to operate and program CompuLab‘s CM-X300 Embedded PC Module, which are listed under Related Documents in this section. Additional chapters are as follows: 2. Overview 3. Functional Description 1.2 CM-X300 Part Number Legend Please refer to the CompuLab Website‘s prices section for information about decoding the CM-X300 part number: http://compulab.co.
CM-X300 CoM 2 OVERVIEW 2.1 Block Diagram Figure 1 CM-X300 Block Diagram WiFi / BT module Bluetooth (BC-4) USB 1 (Host) USB 2 (Host/Slave) WiFi (88W8686) Video Acceleration USB MMC/SDIO USB3 (Slave) USB 2.0 XCVR PXA300/310 MPU, 208 / 624 MHz CPU LCD Interface GPIO x 32 (I2C I/F) 3.
Overview 2.2 CM-X300 Features The "Option" column specifies the configuration code required to have the particular feature. "+" means that the feature is always available. Table 3 CPU, Memory and Busses Feature CPU RAM NAND Flash Disk External local bus AC97 bus Table 4 Intel XScale PXA300/310, 208 / 624 MHz, WMMX2, 2*128K internal SRAM 32 KB I-cache and 32 KB D-cache, WB, 128 MB address space DMA and Interrupt controllers, Timers 64 - 128 MB, DDR, 208 MHz, 16-bit 512 Mbytes, bootable.
CM-X300 CoM WiFi Interface Bluetooth Battery support Implements 802.11b/g wireless connectivity standard Supports Node to Access Point and Multi-Node (w/o access point) methods of connection. (Cannot act as Access Point) Marvell 88W8686 802.11b/g chipset. On-board ceramic chip antenna and connector for external antenna. Bluetooth V2.0+EDR system. CSR BlueCore4-ROM chipset, 2.4GHz band, up to 3Mbps. On-board ceramic chip antenna and connector for external antenna.
Functional Description 3 FUNCTIONAL DESCRIPTION 3.1 Board Layout 3.1.1 Top Side Components Figure 2 shows top side of CM-X300. The relevant top side components are listed in Table 6. Figure 2 CM-X300 Top View Diagram R34 Q2 Q1 U19 U13 U1 X5 U2 ANT2 X4 J3 U3 L6 L7 DS1 U23 J1 Table 6 ANT1 Top Side Components Reference J1 J3 ANT1 ANT2 DS1 Function Bluetooth external antenna connector Wi-Fi external antenna connector Bluetooth antenna Wi-Fi antenna Debug LED 3.1.
CM-X300 CoM Figure 3 CM-X300 Bottom View Diagram Table 7 Bottom Side Components Reference Function P1 P2 CAMI connector A CAMI connector B 3.2 Connectors Pinout 3.2.1 Interface Connectors CAMI signal names, as described in the CAMI Specification as of February 4, 2004, are listed in the tables below. Signal descriptions may be found in the CM-X072 User‘s Manual. CAMI names are provided for easy comparison with previous modules. 3.2.1.
Functional Description Conn-Pin P1-16 P1-17 P1-18 P1-19 P1-20 P1-21 P1-22 P1-23 P1-24 P1-25 P1-26 P1-27 P1-28 P1-29 P1-30 P1-31 P1-32 P1-33 P1-34 P1-35 P1-36 P1-37 P1-38 P1-39 P1-40 P1-41 P1-42 P1-43 P1-44 P1-45 P1-46 P1-47 P1-48 P1-49 P1-50 P1-51 P1-52 P1-53 P1-54 P1-55 P1-56 P1-57 P1-58 P1-59 30-Dec-2010 CM-X300 Signal Name KP_MKOUT1 GPOP122 EXTWAKE# KP_MKOUT3 GPIO124 VCHRG VCC-RTC ONKEY# COM-A-RX# N.C. COM-A-TX# N.C.
CM-X300 CoM Conn-Pin P1-60 P1-61 P1-62 P1-63 P1-64 P1-65 P1-66 P1-67 P1-68 P1-69 P1-70 P1-71 P1-72 P1-73 P1-74 P1-75 P1-76 P1-77 P1-78 P1-79 P1-80 P1-81 P1-82 P1-83 P1-84 P1-85 P1-86 P1-87 P1-88 P1-89 P1-90 P1-91 P1-92 P1-93 P1-94 P1-95 P1-96 P1-97 P1-98 P1-99 P1-100 P1-101 P1-102 P1-103 P1-104 P1-105 P1-106 P1-107 P1-108 P1-109 P1-110 16 CM-X300 Signal Name I2C-DATA I2C-CLK GND DF-A1 DF-A0 DF-A3 DF-A2 VBAT N.C.
Functional Description Conn-Pin P1-111 P1-112 P1-113 P1-114 P1-115 P1-116 P1-117 P1-118 P1-119 P1-120 P1-121 P1-122 P1-123 P1-124 P1-125 P1-126 P1-127 P1-128 P1-129 P1-130 P1-131 P1-132 P1-133 P1-134 P1-135 P1-136 P1-137 P1-138 P1-139 P1-140 CM-X300 Signal Name DF-IO15 DF-IO14 N.C. N.C. VCHRG N.C. N.C. N.C. N.C. N.C. N.C. GND KP_MKIN4 GPIO119 KP_MKIN3 GPIO118 KP_MKOUT5 GPIO4_2 KP_MKOUT4 GPIO125 VCHRG KP_MKIN0 GPIO115 KP_MKIN6 GPIO2_2 KP_MKIN5 GPIO120 N.C.
CM-X300 CoM 18 Conn-Pin CM-X300 Signal Name P2-13 P2-14 P2-15 P2-16 P2-17 P2-18 P2-19 P2-20 P2-21 P2-22 P2-23 P2-24 P2-25 P2-26 P2-27 P2-28 P2-29 P2-30 P2-31 P2-32 P2-33 P2-34 P2-35 P2-36 P2-37 P2-38 P2-39 P2-40 P2-41 P2-42 P2-43 P2-44 P2-45 P2-46 P2-47 P2-48 P2-49 P2-50 P2-51 P2-52 P2-53 P2-54 P2-55 P2-56 P2-57 P2-58 P2-59 P2-60 P2-61 P2-62 P2-63 P2-64 P2-65 P2-66 P2-67 P2-68 P2-69 MMC_CMD1 GND MMC_CMD0 MMC_CLK N.C. N.C.
Functional Description Conn-Pin P2-70 P2-71 P2-72 P2-73 P2-74 P2-75 30-Dec-2010 CM-X300 Signal Name I2C_GPIO3_5 TS-XM I2C_GPIO3_7 TS-YM GND CIF_DD2 GPIO41 P2-76 CIF_DD3 GPIO42 P2-77 CIF_DD1 GPIO40 P2-78 CIF_DD4 GPIO43 P2-79 VBAT P2-80 CIF_DD5 GPIO44 P2-81 CIF_DD0 GPIO39 P2-82 CIF_DD6 GPIO45 P2-83 CIF_DD9 GPIO48 P2-84 CIF_DD7 GPIO46 P2-85 CIF_DD8 GPIO47 P2-86 GND P2-87 CIF_FV GPIO52 P2-88 CIF_MCLK GPIO49 P2-89 SYS_EN P2-90 CIF_LV GPIO51 P2-91 P2-92 VCHRG N.C.
CM-X300 CoM Conn-Pin CM-X300 Signal Name P2-114 P2-115 P2-116 P2-117 P2-118 P2-119 P2-120 P2-121 P2-122 P2-123 LCD-DE VCHRG LCD-R3 LCD-R5 LCD-R4 N.C. N.C.
Functional Description 3.3.2.1 Wireless LAN Specifications The CM-X300‘s wireless LAN‘s 802.11b RF specifications are listed in Table 10; 802.11g specs in Table 11. Table 10 11.288b RF System Specifications Parameter Test Condition Transmit Power Output Maximum Receive Level Transmit Frequency Offset 1 Mbps, 8% PER 2 Mbps, 8% PER 5.5 Mbps, 8% PER 11 Mbps, 8% PER PER<8% Low, Middle, High Channels Spectral Mask Max. TX Power Error Vector Magnitude Carrier Suppression Max. TX Power @ 11Mbps Max.
CM-X300 CoM 3.3.3.1 Wireless LAN Specifications CM-X300‘s Bluetooth RF specifications are listed in Table 12. Table 12 Bluetooth RF System Specifications Parameter Test Condition Typical Value Units 3 -84 -87 -80 dBm dBm dBm dBm 5 kHz 10 10 13 kHz kHz kHz 13 kHz 165 kHz 168 kHz 1.02 654 kHz Transmit Power Output 1 Mbps, 0.1% BER 2 Mbps, 0.1% BER 3 Mbps, 0.
Functional Description 3.3.4.1 Accessing DM9000A The drivers for the Ethernet controller are provided in all SW support packages. The following description is for system-level programmers only. There are two addressing ports for accessing DM9000A through the host interface. One port is the INDEX port and the other is the DATA port. In the CM-X300 the INDEX port is at the address 2x08000010 and the DATA port is at the address 2x08000014.
CM-X300 CoM Figure 4 Magnetic Interconnect Schematic Figure 5 DC Source for Magnetic Center Taps 3.3.5 Serial Ports CM-X300 incorporates 3 UARTs: one full function UART, one RX-TX only (console) UART and one partial-function UART. All three UARTs share the same feature list, baud rates and use the same programming model.
Functional Description 3.3.5.1 7- or 8-bit characters Even, odd, or no parity detection 1 stop-bit generation Baud-rate generation of 9.6K to 3.
CM-X300 CoM COM-A-TX# 3.3.5.3 O Serial Data Out: transmits the serial data from the internal serial port controller to the external serial device or DCE. Partial-Function UART This is the CPU‘s UART2. The interface is routed to the CAMI COM-D serial port and uses TTL-levels signaling. The port‘s pin descriptions are listed in Table 17. Table 17 3.3.
Functional Description Table 19 LB-BE[1:0]# O LB-RDY I Local Bus Signals (NFC) CM-X300 Signal Name DF-IO[15:0] DF-CS[1:0]# DF_CLE_nOE DF_ALE_nWE DF-RE# DF-WE# DF-RB# 3.3.6.2 Data byte enable. nBE0 corresponds to DF-IO[7:0] nBE1 corresponds to DF-IO[15:8] 0 = Do not mask out corresponding byte 1 = Mask out corresponding byte Variable-Latency I/O Ready signal for inserting wait states.
CM-X300 CoM Table 21 If there is stable keypad activity for a period greater than the specified key debounce interval while the automatic-scan-on-activity is enabled, completion of the scan generates an interrupt. If the automatic-scan is enabled, user software determines when to initiate an automatic scan. This option does not generate an interrupt.
Functional Description Table 22 LCD Signals CM-X300 Signal Name 3.3.8.1 Type LCD-R[5:1] O LCD-G[5:0] O LCD-B[5:1] O LCD-LP LCD-FRM LCD-SCK LCD-DE O O O O Description Red channel data for TFT panels. Bit 0 of the panel‘s red channel should be connected to GND. Green channel data for TFT panels. Blue channel data for TFT panels. Bit 0 of the panel‘s blue channel should be connected to GND. HSYNC for TFT panels. VSYNC for TFT panels. Pixel clock.
CM-X300 CoM bandwidth needed exceeds the total available memory bus bandwidth, visible video artifacts may be seen on the LCD panel.
Functional Description Pixel clock frequency is a parameter of the chosen resolution and frames per second, as well as of the LCD-specific parameters, such as pixel clock wait states at the beginning and end of each line, the number of line clocks inserted in the beginning and end of each frame. Here's an example of some common video modes and their corresponding pixel clocks: http://www.engr.udayton.edu/faculty/jloomis/altera/DE2/vga.
CM-X300 CoM 3.3.9.2 USB Interfaces Routing Table 23 below describes USB interfaces routing differences between C624 and C624M module configurations. Table 23 USB Interfaces CAMI USB Interface USB1 USB2 USB3 3.3.9.3 CM-X300-C625 CM-X300-C625M USB Host Controller (differential port1 IF on PXA300) USB Host Controller or USB Device Controller (OTG diff port 2 IF on PXA300) USB 2.0 Device Controller (UTMI IF) on PXA300 USB Host Controller (single ended port 3 IF on PXA310) USB2.
Functional Description Table 26 3.3.10 USB3 CAMI Port Signals CM-X300 Signal Name Type {USBD-P, USBD-N} I/O Description USB 2.0 Device Data Differential pair that connects to the USB 2.0 device controller. MMC/SD/SDIO Controller The Multimedia Card (MMC) and Secure Digital (SD/SDIO) controller (MMC/SD/SDIO controller) provides a software-accessible hardware link between the processor and the MMC stack (a set of memory cards).
CM-X300 CoM Table 28 SPI Mode Signals CM-X300 Signal Name Type MMC_CLK MMC_CMD0 MMC_CMD1 MMC_DAT0 MMC_DAT1 MMC_DAT2 MMC_DAT3 O O O I I O O 3.3.11 GPIO 3.3.11.
Functional Description When programmed as an input, a GPIO port can also serve as an interrupt source. At the assertion of all resets, all ports are configured as inputs and remain inputs until they are configured either by the boot process or by user software. The direction of the GPIO ports is controlled by writing to the CPU‘s GPIO Pin Direction register (GPDR2).
CM-X300 CoM Name 36 Address GPCR2 0x40E0_002C GRER2 0x40E0_0038 GFER2 0x40E0_0044 GEDR2 0x40E0_0050 GSDR2 0x40E0_0408 GCDR2 0x40E0_0428 GSRER2 0x40E0_0448 GCRER2 0x40E0_0468 GSFER2 0x40E0_0488 GCFER2 0x40E0_04A8 Description GPIO Pin Output Clear Register 2. An output port is cleared when a 1 is written to the corresponding bit within the GPCR2 (write-only register; reads return unpredictable values). 0 = Port level unaffected.
Functional Description Table 34 CPU GPIO DC Characteristics Symbol Parameter Low level input voltage High level input voltage High level output voltage Low level output voltage VIL VIH VOH VOL RPULLUP, RPULLDO Condition Min Typ Max Unit VCC typ = 3.2V -0.3 – 0.2 x VCC V VCC typ = 3.2V 0.8 x VCC – VCC + 0.3 V IOH = -1.5 to -18 mA 0.9 x VCC – VCC V IOH = -1.25 to -15 mA VSS – 0.1 x VCC V 20 45 100 kOhm Pull-up and pulldown resistance WN 3.3.
CM-X300 CoM CM-X300 Signal Name Type CIF_FV I/O CIF_LV I/O 3.3.13 Audio Subsystem 3.3.13.1 Audio I/O Description Frame start or alternate synchronization signal used by the sensor to signal frame readout or as an external vertical sync. For CIF_PCLK speeds > 26 MHz, the sensor CIF_FSYNC signal must not be active until at least 2 pixel clocks after the last valid data of a frame. This pin may be defined as GPIO52 in a camera-less application.
Functional Description Table 38 3.3.15 Touch Panel Interface Signals CM-X300 Signal Name Type TS-XP TS-YP TS-XM TS-YM AI AI AI AI Description X+ (Right) Y+ (Top) X- (Left) Y- (Bottom) Power The CM-X300 connects to power sources through the dedicated pins on the CAMI connectors listed in the Table 39 below.
CM-X300 CoM Table 41 System Signals CM-X300 Signal Name Type WP1# I RST-IN# I/OD EXTWAKE# I ONKEY# I IRQ I BOOTENA# I RST-OUT# OD SYS_EN O EXT_TBAT I 3.3.17 I2C Bus Table 42 I C Signals 3.3.18 Description Hardware write protect for the the entire onboard Data Flash. Prevents all program/erase operations. Pulled up to 3.3V internally. Connect to GND to write-protect. Reset input to CPU and power-on reset output. Pulled up to 3.3V Processor‘s wakeup signal. Pulled down to GND.
Functional Description 3.3.18.1 CM-X300 Signal Name Type SSPTXD3 SSPRXD3 O I Description Synchronous Serial Protocol Transmit Data. Serial data out. Synchronous Serial Protocol Receive Data.Serial data in. SSP Features The SSP port features are: 3.3.18.2 Directly supports Texas Instruments* Synchronous Serial (SSP) and Motorola* Serial Peripheral Interface (SPI). The Inter-IC Sound (I2S) protocol is supported by programming the Programmable Serial Protocol (PSP).
CM-X300 CoM 3.3.19.1 PWM Features 3.3.19.2 Four pulse-width modulated signal channels Enhanced period controlled through 6-bit clock divider and 10-bit period counter 10-bit pulse control PWM Operation Figure 7 shows the block diagram for the PWM control logic. Figure 7 PWM Block Diagram To program the PWM controller, determine the period and pulse-width values. The period value is based on two registers, PWMPCR2 and PWMCR2.
Functional Description Figure 9 For PWMPCRx[PV] values 0x005 and larger—After a register value is altered, the PWM_OUTx signal changes when the previously programmed waveform cycle is complete. For PWMPCRx[PV] values less than 0x005—After a register value is altered, the PWM_OUTx signal changes after two waveform cycles Effect of PWMCR2 Settings Programming PWMCRx[PRESCALE] configures the prescaled counter clock. Two timing examples are provided in Figure 9.
CM-X300 CoM Use the following equation to calculate the cycle time of the scaled counter clock: Scaled counter clock cycle time = 76.9 ns x (PWMCRx[PRESCALE] + 1) Both the period and the duty cycle of the PWM are based on the scaled counter clock cycle time. The PWMx_OUT signal is asserted for the number of scaled counter clock cycles equal to PWMDCRx[DCYCLE].
Functional Description 3.3.19.6 PWM Control Register (PWMCRx) The PWM Control register (PWMCRx), defined in Table 47, configures the behavioral characteristics of the PWM shutdown response and the divisor for the input clocks to the PWM control unit that configures the frequency of the scaled counter clock. This is a read/write register. Ignore reads from reserved bits. Write 0b0 to reserved bits. Table 47 3.3.19.
CM-X300 CoM Table 49 46 PWM Period Control Register Bits Access Name 31:10 – – 9:0 R/W PV Description Reserved Period Value: The value of scaled clock cycles per cycle of PWMx_OUT plus one. If all zeros are written to this register the signal remains high. CM-X300 Reference Guide Rev 1.
Baseboard Interface 4 BASEBOARD INTERFACE 4.1 CAMI Connectors The CM-X300 connects to the external world through P1, P2 – 0.6 mm pitch 140-pin connectors. 4.1.1 Connectors Type and Layout Table 50 CAMI Connectors Reference Mfg. CM-X300 connector P/N Baseboard (mating) connector P/N P1, P2 AMP 1-5353183-0 1-5353190-0 or CON140 Mating connectors and standoffs are available from CompuLab, see [prices] >> [accessories] links in the CompuLab's website.
CM-X300 CoM 4.2 Mechanical drawings CM-X300 Top View Q2 R3 4 Q1 Figure 10 U1 9 X5 U1 3 U1 U2 ANT2 X4 J3 L6 U3 L7 J1 U2 3 ANT1 Figure 11 CM-X300 Bottom (X-Ray view – as aeen from the top side) 140 2 X1 P1 1 139 140 2 P2 1 U20 U21 139 U4 U15 X6 U16 C1 U14 U5 1. All dimensions are in millimeters 2. Height of all components except X5 and C1 is <2mm 3. The height of X5 is 2.5mm typ., of C1 is 2.0mm typ. 4.
Baseboard Interface 4.3 Baseboard Design Guidelines Assure that all power pins are connected as specified in ―Power‖ section of this manual. GND must be implemented by plane, rather than traces. It is recommended to put several 100 nF and 10/100 uF capacitors between VBAT/VCHRG and GND near the mating connectors. It is recommended to connect 3 out of the 4 standoff holes of the baseboard to GND, in order to improve EMC.
CM-X300 CoM In order to avoid possible sources of disturbance, it is strongly recommended to start with minimal system and then add/activate off-board devices one by one. Check for existence of soldering shorts between pins of mating connectors. Even if signals are not used on the baseboard, shorting them on the connectors can disable module's operation. Initial check can be performed using microscope.
Operating Temperature Ranges 5 OPERATING TEMPERATURE RANGES The CM-X300 is available with three options of operating temperature range. Table 52 30-Dec-2010 CM-X300 Temperature Range Options Range Temp. Commercial 0o to 70o C Extended -20o to 70o C Industrial -40o to 85o C Description Sample cards from each batch are tested for the lower and upper temperature limits. Individual cards are not tested. Every card undergoes short test for the lower limit (-20o C) qualification.
CM-X300 CoM 6 POWER CONSUMPTION Typical power consumption has been measured on module inserted into SB-X300 carrier board with no peripherials connected and 3.05V power source connected to the VBAT rail. Measurements do not include power drawn by the SB-X300 base board. Table 53 CM-X300 Power Consumption (BT and Wi-Fi enabled) Parameter Value, mA Imax Iidle Isusp 470 350 16.