Service manual

ManualsBrandsBenQ ManualsProjectorPB6200 - XGA DLP Projector

DLP PROJECTOR

SERVICE MANUAL

MODEL：PB6100 / PB6200

CAUTION

BEFORE SERVICING THE PROJECTOR,

READ THE SAFETY PRECAUTIONS IN THIS MANUAL.

Summary of content (122 pages)

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DLP PROJECTOR SERVICE MANUAL MODEL：PB6100 / PB6200 CAUTION BEFORE SERVICING THE PROJECTOR, READ THE SAFETY PRECAUTIONS IN THIS MANUAL.
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Index 1. Safety Precautions -------------------------------- 3 2. Engineering Specification---------------------- 4 3. Spare Parts List ---------------------------------- 32 4. Block Diagram ------------------------------------ 36 5. Packing Description ---------------------------- 44 6. Factory OSD Operation ------------------------ 50 7. Firmware upgrade procedure --------------- 57 8. RS232 Communication Protocol ----------- 61 9. Trouble Shooting Guide ----------------------- 73 10.
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3. Spare Parts List Model : PB6100 Item Component Description Type 1 42.J8618.001 U/C PC+ABS PB6100 R 2 55.J7612.001 PCBA KEYPAD BD PB7200 BENQ850 2 3 54.J8612.001 BALLAST PHG201G16 PB6100 R 4 60.J8605.001 ASSY Lower Case PB6100 R 5 23.10102.001 BLOWER 12V 50*50*20MM ADDA R 6 60.J8617.001 ASSY LAMPBOX PB6100 R 7 23.10103.001 FAN 12V 70*70*25AXIAL ADDA R 8 60.J8604.001 ASSY R/C PB6100 R 9 55.J8608.001 PCBA REAR IR BD PB6100 2 10 65.J8602.
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Model : PB6100 Item Component Description Type 21 31.J8601.001 BADGE AL PLATE PB6100 R 22 60.J1334.001 ASSY CAP LENS SL700X R 23 60.J8603.001 ASSY F/C PB6100 R 24 55.J8611.001 PCBA PFC BD PB6100 2 25 55.J8613.001 PCBA FAN BD PB6100 2 26 65.J5003.001 FOOT ADJ DX850 R 27 44.J0502.005 CTN 415*325*255 PB6100/BENQ VI R 28 47.J8605.001 CUSHION FRONT EPE PB6100 R 29 47.J8606.001 CUSHION REAR EPE PB6100 PB6100 R 30 50.72920.011 C.A MIN-DIN 4P S-VIDEO W/S 150 R 31 50.J0508.
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Model : PB6200 Item Component Description Type 1 55.J8501.001 PCBA MAIN BD PB6200 2 2 42.J8618.001 U/C PC+ABS PB6100 R 3 55.J7612.001 PCBA KEYPAD BD PB7200 BENQ850 2 4 54.J8612.001 BALLAST PHG201G16 PB6100 R 5 55.J5020.001 PCBA EMI BD DX850 2 6 60.J8605.001 ASSY L/C PB6100 R 7 55.J8608.001 PCBA REAR IR BD PB6100 2 8 23.10103.001 FAN 12V 70*70*25AXIAL ADDA R 9 60.J8607.001 ASSY DOOR PB6100 R 10 23.10102.001 BLOWER 12V 50*50*20MM ADDA R 11 60.J8617.
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Model : PB6200 Item Component Description Type 21 55.J8611.001 PCBA PFC BD PB6100 2 22 55.J8613.001 PCBA FAN BD PB6100 2 23 65.J5003.001 FOOT ADJ DX850 R 24 44.J7601.051 CTN AB PB6100/BENQ(VI) R 25 45.L2701.011 LBL CTN 120*100 BLUE FP559 R 26 47.J8605.001 CUSHION FRONT EPE PB6100 R 27 22.91007.001 SKT PLUG 2/3P W/G R 28 27.01818.000 CORD SVT#18*3C 10A125V 1830US R 29 44.J0501.011 CTN ASSY 350*240*48 7765P R 30 50.72920.011 C.A MIN-DIN 4P S-VIDEO W/S 150 R 31 50.J0508.
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4. Block Diagram PB6100 DMD projector being using the SGA DMD Engine made by BENQ, it included front end circuitry that digitizes and scaling processes for the input analog VGA and TV signals. As shown, in figure below the front end circuitry consists of : 1. Frond end Circuitry 1.1 Power supply module include PFC and DC/DC portion. DC/DC portion provide 12V, 5V and 3,3V for whole system. 12V Lamp Fan1 PFC Lamp Power IGNITOR AC IN POWER SUPPLY Module Lamp Fan Power Fan DC to DC EMI Filter 12V,5V,2.
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From Power Supply Regulator(3.3v) 12V,5V,2.5V EEPROM (16K bit) ThERMAL IC SENSOR Scaler (memory +cpu+osd) RGB888 Signal To DMD Driver Power(12V,5V,2.5V) To DMD Driver Control Signal To DMD Driver D-Sub Input AD Converter S-Video& RCA input DMD driver board that transfer PW166 scaler output RGB888 signal to DMD chip acceptable signal for driving DMD mirror operation. The relate diagram as below: RAMBUS CLOCK GEN 400mHz RAMBUS RDRAM Data & Address 2.
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3. Whole system block diagram is show as below: Lamp Module Optical Device PFC Optical Engine DMD Lamp On EMI Filter Power Board and Ballast Color Wheel DC/DC Ballast 2.
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Block Diagram Below is the simple block diagram of PB6100 Main Board . D_SUB I2C I2C Analg Flat Panel Interface AD9883 EEPROM RGB888 signals Address Control Signals Image Processor PW166 Flash Data I2C S-Video RCA Video Decoder SAA7118 YUV 422 Control Signals Clock GEN Clock signal RGB 888 Signals I2C Control Signals DMD Driver As the diagram shown above , here is the function of every discrete blocks .
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There are some other interface signals related to AD9883 SOGIN – Sync On Green input from Image Processor , the signal enable the PB6100 support the very special VGA input signal . GCOAST – Input signal from Image Processor , the signal enable the PB6100 support the Machintosh analog input format . GCLK – Output to Image Processor as Pixel Clock , providing the reference clock for Image Processor . GHS – Providing the Horizontal Synchronization signal to Image Processor .
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abnormal status , it will disable lamp ignition . POWERON – Output to power to enable the other power source into normal working situation . LAMPLIT – Input signal as an indicator that the Lamp is ON or OFF LED1, LED2 – Output to enable the LED ON or OFF . IRRCVR0 – System IR input to CPU as remote control signals . MCKEXT – Memory clock to CPU . DCKEXT – Data clock to for Scaling . I2C_SDA , I2C_SCL – I2C format data transfer line . . EEPROM Store the system information for user friendly . .
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Sensor BD: The Sensor BD provides the color wheel index signal to DMD BD. The CWINDEX shall indicate the beginning of the red light on the DMD device. The phase of the display data on the DMD based on the CWINDEX signal. It can be configured to delay the CWINDEX for electronic alignment of the color wheel. The timing of CWINDEX and the delayed CWINDEX is shown in Figure 1.
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PB6100 Lamp on Sequence Signal Voltage Change POWERON LowÆHigh Description 1. This signal should go from low to high after all the DC supplies are within spec. Then RESETZ can go high. 2. After the power key pressed 3 second continuously, the POWERON signal will activate. RESETZ LowÆHigh DMD is working, when the DMD reset. LAMPEN LowÆHigh Lamp lights up. LAMPLIT LowÆHigh Indicate ”Lamp on”. PB6100 Normal Lamp off Signal Sequence Voltage Change Description RESETZ HighÆLow DMD is off.
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5.
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6. Factory Menu 1. How to enter factory menu: I. Hold press "UP" button until the "Lamp hours info." OSD display on bottom-right of screen (Fig-1) (Fig-1) Lamp Hours Info II. Press keypad and key simultaneously again, then enter Factory menu.
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2. Factory layer: I. DMD layer (Fig-3): (Fig-3) DMD layer 1. CW delay: Adjust color wheel delay.(Note this value before upgrade software) 2. White peak: Adjust DMD white peak. In PC mode default value set 10, in Video mode is 0. Software auto set this value as source find. 3. DLP Brightness: Adjust DLP Brightness. Default setting is 36.Do not change this value. 4. DLP Contrast: Adjust DLP Contrast. Default setting is 30.Do not change this value. 5. Burn-In Hour: set how many hours to burn-in.
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II. 1. 2. 3. 4. 5. 6. III. ADC layer (Fig-4): (only available when input source is analog RGB) (Fig-4) ADC layer ADC Brightness: ADC brightness auto calibration black. ADC Contrast: ADC contrast auto calibration white. ADC Offset RGB: value to tell you calibrate result. ADC Gain RGB: value to tell you calibrate result. Fac Brightness: adjust default brightness value in source PC. Fac Contrast: adjust default contrast value in source PC.
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1. PbPr: enter PbPr color control Layer. When Source is YPbPr (Never Change these setting) (Note these values Before Upgrade Software) PbPr G Offset : combine with user OSD brightness in YPbPr PbPr G Gain: combine with user OSD contrast in YPbPr PbPr R Offset: offset of color red PbPr G Offset: offset of color green PbPr R Gain: saturation R PbPr B Gain: saturation B 2.
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11500 B :gain of color blue while color temp is 11500 3. PC 9300 and Video 9300: 9300K submenu. (Never Change these setting) PC 9300 R :gain of color red while PC color temp is 9300 PC 9300 G :gain of color green while PC color temp is 9300 PC9300 B :gain of color blue while PC color temp is 9300 Video 9300 R :gain of color red while Video color temp is 9300 Video 9300 G :gain of color green while Video color temp is 9300 Video 9300 B :gain of color blue while Video color temp is 9300 IV.
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5. V. Curtain Blue: unit display full color blue. Lamp layer (Fig-6): (Fig-6) Lamp layer 1. Interpolation: De-interlace Mode 2. Filter: system auto select Filter. 3. Lamp Hour: value to tell you lamp usage hours. 4. Usage Hour: value to tell you unit usage hours. 5. Fac Lamp Hours: Record all of the amp usage hours 6. Data Reset: Reset all data to default include factory assign value. Never try to reset all data. VI. Others layer (Fig-7): 1. 2.
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3. 4. 5. 6. VII. Blue value: adjust here to check DMD fail pixel. Scaling: tell you what scaling mode is using now. Pc/PbPr Mode: index of input timing RS232: Enable / Disable RS232 control FAN Layer. T1-DMD: DMD sensor temperature T2-Lamp: Lamp sensor temperature T3-Blwr: Blower sensor temperature F1-Lamp:Lamp fan speed in RPM F2-Blst: Blaster fan speed in RPM F3-Blwr : Blower fan speed in RPM Manual Fan Speed: Change fan speed by manual.
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7. Firmware upgrade procedure PB6100/PB6100 Download Procedure Hardware required 1. 2. 3. 4. 5. 6. 7. 8. D-sub download cable (full ping D-SUB P/N : 50.J2402.201) Download board ( P/N : 55.J1316.001 ) PS2 Download cable from download BD to PC ( P/N : 50.J0510.5D1 ) (Cable/RS232D MD8PM/DS9PF 1800MM) Adaptor for Download BD ( DC12 V) DVD player with YPbPr (Progressive) output PC timing/pattern generator Personal computer or laptop computer Software required 1. FlashUpgrader.exe (or FlashUpgraderNT.
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2. Record all Color Temperature values in factory page 3. Fig. 2 3. 4. Power down the projector and turn the power switch off after cooling. Setup the download board as Fig. 3 PS2 Download cable to PC P/N : 50.J0510.5D1 Download BD P/N : 55.J1316.001 D-Sub connector to Projector P/N : 50.J2402.201 Power supply DC 12 V Fig. 3 5. Connect the D-Sub to PC input of Projector.
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6. Run FlashUpgrader.exe and open the file pwSDK.inf. You can browse to locate it. Select the correct COM port and use 115200 as the BAUD rate.(as Fig. 4) Fig. 4 7. Press the “Flash” button , and then turn on the power switch. (as Fig. 5) Fig. 5 8. Now the progress bar in the FlashUpgrader should be running. 9. Download is complete ,Pls turn off power switch , and turn ON power switch. 10. Power on projector and the factory settings should be restored.
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Calibration procedure 1. Use any video pattern generator to output XGA 60Hz PC timing with 32 grayscale pattern. Enter the factory OSD page 2 and execute ADC Brightness and ADC Contrast.(as Fig. 6) Fig. 6 2. Restore CW delay value and color temperature values. Verification Check the version number in the factory OSD page 1.(as Fig.
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8. RS232 Communication Protocol / Codes External Communication Protocol External communication protocol include two parts：A. setup connecting, B. send command. BenQ default Serial Port : Baud Rate: 19200 Parity: none Data bits: 8 Stop bits: 1 Flow Control:none A.
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a.
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e. Packet to Target (BenQ PB6XXX) structure (Table 3) Packet Header Packet Payload Byte0 0xBE Byte1 0xEF Magic Number Byte2 0x01 Packet Type Byte3 0x05 Packet size (Low) Byte4 0x00 Packet size (High) Byte5 0xA9 CRC (Low) Byte6 0xC6 CRC (High) Byte7 0x00 System Info Type Byte8 0x00 Byte9 0x00 Byte10 0x00 Object ID Byte11 0x00 Level Version Number Table 3 B. Send Command 1. Introduction Command packets consist of “Header” and “Payload”.
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The Packet Header size is fixed at seven bytes (Intel byte ordering is used). The following code fragments are taken from these source files The Packet Header definition is shown below: typedef struct { BYTE ePacketType; // type of the payload WORD nPacketSize; // size of the payload WORD nCRCPacket; // CRC for the entire packet } PACKET_HEADER; Magic Number The Magic Number is a fixed value that is used to insure packet alignment if there are partial packets received or bytes lost.
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2. Packet Payload Definition Event Packet Type The Event packet is used by the host system to send virtual events (such as Zoom, Source, Auto Adjust, etc.) to the target system. Packet payload size is 6 bytes. Byte Field Name 0-1 Field Value Virtual Event Description Virtual Event ID as defined through Configurator 2-5 Parameter Parameter that can be associated with the event. .
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13-16 17-20 21-24 Operation Value of The Minimum Value of the set for operation minimum. command. Operation Value of The Maximum Value of the set for operation maximum command. Operation Value of The Increment Value of the set for operation Increment command.
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3. Send Command PC BenQ PB6XXX Host System a Packet to Target Target System => <= ACK b Figure 4 a. The structure of Command (EX.
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C. Serial Communication Cable and Parameters For external serial communication from a computer to BenQ projector, BenQ recommends manfactures use RS-232 communations over a straight through serial cable a 9 pin female D-sub9 connector. The standard D-sub9 connector on the computer is a male connector, and BenQ projector, too. The wiring between the computer and BenQ projector is a straight through cable.
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D.
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Command List Event Packet Type command: Command Packet Header (7 bytes) Packet Payload (6 bytes) Power BE EF 02 06 00 13 CE AA 00 00 00 00 00 Auto BE EF 02 06 00 F7 C8 8E 00 00 00 00 00 Input select BE EF 02 06 00 C4 C8 8D 00 00 00 00 00 Menu BE EF 02 06 00 26 C9 8F 00 00 00 00 00 Exit BE EF 02 06 00 FE CA 97 00 00 00 00 00 Zoom + BE EF 02 06 00 AD CD B4 00 00 00 00 00 Zoom - BE EF 02 06 00 7C CC B5 00 00 00 00 00 PIP Source BE EF 02 06 00 37 C6 CE 00 00 00 00 00 Freeze BE EF 02 0
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S-Video / Composite Video Picture Controls Command Packet Header (7 bytes) Packet Payload (25 bytes) Brightness + BE EF 03 19 00 E9 18 03 35 02 CC CC 00 00 00 00 CC x16 Brightness - BE EF 03 19 00 87 B2 04 35 02 CC CC 00 00 00 00 CC x16 Contrast + BE EF 03 19 00 16 FC 03 36 02 CC CC 00 00 00 00 CC x16 Contrast - BE EF 03 19 00 78 56 04 36 02 CC CC 00 00 00 00 CC x16 Color + BE EF 03 19 00 83 A1 03 37 02 CC CC 00 00 00 00 CC X16 Color - BE EF 03 19 00 ED 0B 04 37 02 CC CC 00 00 00 00 CC x1
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CC CC CC CC CC CC CC CC CC CC CC CC Mid-Left BE EF 03 19 00 EC 26 01 43 02 CC CC 01 00 00 00 03 00 00 00 CC CC CC CC CC CC CC CC CC CC CC CC Mid-Center BE EF 03 19 00 DE 64 01 43 02 CC CC 01 00 00 00 04 00 00 00 CC CC CC CC CC CC CC CC CC CC CC CC Mid-Right BE EF 03 19 00 4E A5 01 43 02 CC CC 01 00 00 00 05 00 00 00 CC CC CC CC CC CC CC CC CC CC CC CC Lower-Left BE EF 03 19 00 BF E5 Lower-Center BE EF 03 19 00 2F 24 Lower-Right BE EF 03 19 00 DB 61 01 43 02 CC CC 01 00 00 00 06 00 00 00 CC CC
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9. Trouble Shooting Guide Optical Engine No. Item Trouble Shooting Guide Brightness 1. Change lamp 2. Check overfill size: If overfill too large, re-install SL and AL to ensure correct position 2 Uniformity 1. If Uniformity is within 3% of spec: Change lamp 2. Check FM installation 3. Check overfill size: If overfill too small, re-install SL and AL to ensure correct position 3 FOFO Contrast 1. Clean DMD 2. Clean PL 4 ANSI Contrast 1. Clean PL 2. Clean DMD 3.
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Main board 1.chk voltage input from F/B : 2.5V,5V,12V 2.chk oscillator Y2,Y3 output frequency (16.257MHz,10MHz) 3.chk MCLK(U24-5,130MHz) and DCLK(U25-5,40MHz) 4.chk U17 whether S/W inside or bad soldering 5.change U22(bad soldering) 6.chk Reset IC (U14) 7.chk Abnorm al signal 8.chk Resetz(RN25-5),Poweron(RN25-6) ,DVS(RN18-3),DEN(RN181),DHS(RN18-2),DCLK(RN18-4) System no work Yes No No data 1.chk output from U15(RN6,RN7,RN8,RN9,RN10,RN11) [graphics input] 2.
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DMD Driver Start Yes Power Voltage 1.chk J702,2.5V(4,,5,6),5V(3),12V(1) 2.chk bead L710-L714,L44 No Yes DDP 1000 function No Yes 1.LAMPEN Signal to Ballast. 2. 3.5s after LAMPLIT,DMD Become Active and Display an Image . No 1.chk clock frequency (unit:MHz) a.Y901(30)b.Y5(20) C.UY1(100) C.Motor Controller(8.33) 2.chk ACTDATA,POWERON,RESETZ,CLKIN,HSYNC, VSYNC,SYNCVALID from Front End 3.chk CW spinning frequency 120Hz , if wrong, chk MTRDATA , MTRCLK , MTRSELZ Peripheral Hardware .
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Smaller boards FAN/BD No Fan control: 1.chk the voltage of Q F1 (5,6,7,8) 2.chk the fan voltage U502(2,15),U503(8) 3.check Y501(32.768kHz) No 5V 1.Check Q 701 & therm al Breaker Yes Keypad function No LED dark 1.chk LED voltage from J1 2.chk the m ounting direction of LEDs No work 1.chk buttons contact to PCB Yes Rear Front IR function No 1.chk U1 voltage source(5V) 2.
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DC-DC BOARD Appendix: Abbreviations PWR M/B F/C D/B FPC K/B R/B CW S/W S/B F/B AL SL FG LP FM CM PL Power supply module Main board Front End Circuit DMD Driver Circuit FPC transmission board Keypad board Rear IR board Color wheel Software Sensor board Fan board Aspherical Lens Spherical Lens Front Glass Light Pipe Fold Mirror Concave Mirror Projection Lens 77
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10. CUSTOMER ACCEPTANCE CRITERIA CONTENT 1.0 SCOPE 2.0 PURPOSE 3.0 APPLICATION 4.0 DEFINITION 5.0 CLASSIFICATION OF DEFECTS 6.0 CLASSIFICATION OF DEFECTIVES 7.0 INSPECTION STANDARD 8.0 GENERAL RULES 9.0 TEST CONDITIONS 10.0 TEST EQUIPMENTS PART Ⅰ INSPECTION CRITERIA 1. PACKING, MARKING AND ACCESSORY 2. APPEARANCE ON VISIBLE PARTS 3. INSTALLATION 4. FUNCTION 5.
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1.0 SCOPE This document establishes the general workmanship standards and functional acceptance criteria for PROJECTOR produced by BENQ. 2.0 PURPOSE The purpose of this publication is to define a procedure for inspection of the PROJECTOR by means of a customer acceptance test, the method of evaluation of defects and rules for specifying acceptance levels. 3.
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6.0 CLASSIFICATION OF DEFECTIVES A defective is a product which contains one or more defects. The defective will be classified into following classes: 6.1 Critical defective A critical defective contains one or more critical defects and may also contain major and/or minor defects. 6.2 Major defective A major defective contains one or more major defects and may also contain minor defects but contains no critical defect. 6.
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8.0 GENERAL RULES 8.1 The inspection must be carried out by trained inspectors who have knowledge about the product. good 8.2 The inspection must be based upon the documents concerning the completely assembled and packed product. 8.3 When more defects appear with the same unit only the most serious have to be taken into account. defect 8.
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10.0 TEST EQUIPMENTS 10.1 Pentium with 32MB of system memory , 64M RAM and above are recommended. 10.2 Win98 or later Operation Environment 10.3 VGA or any Windows compatible display with a resolution of at least 640x480 pixels, and set to high color or true color mode. 10.4 Quantum card/Chroma & Test pattern files 10.5 Dark room 10.6 29 points optical measure equipment 10.7 Pattern generators 10.8 DVD player 10.
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PART Ⅰ INSPECTION CRITERIA ■ Packing, marking and accessory △ Inner packing material broken. minor △ Carton damaged with hole over 1.5 cm in diameter. minor △ Carton crashed with dent over 5 cm in diameter. minor △ Printing of carton is illegible. minor △ Broken packing bag minor ☆ Spec. label's serial number not the same as carton label's. Major ☆ Packing model not the same as carton. Major ☆ Marking missing/wrong. Major ☆ Accessory shortage/wrong.
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■ Function △ Abnormal sound during projection(from 50 cm). minor ☆ LED won’t light / No power / can't work. Major ☆ Other function test please refer to Note 2. ■ Safety defect class ☆ Any item which violates the approved safety standard. major ★ Electrical shock or smoke. Critical Note 1 : Please refer to attachment 1. Note 2 : Please refer to attachment 2. Attachment 1 Scratch Acceptance Any scratch which exceeds the maximum allowance is treated as a minor defect. 2 Spec. (mm ) 0.
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Diagram - A1 Definition of Projector's sides 85
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Attachment 2 Quality Specification of PB6100 Following item’s spec. will base on Engineering spec. Item 1. Brightness Spec Minimum 2. Uniformity Minimum Remarks 1120 lumens major 50 % 3. ANSI Contrast Ratio 4. FOFO contrast Ratio major 150:1 700:1 major major 5. Screen Size For Testing 60” at 2m major 6 .Focus Range 1.5~6m major 7. Keystone Distortion <1.0% 8. Audible Noise Level major Typical 34dBA at 25°C Maximum 35dBA at 25°C major IEC - 06 9.
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18.Color Temprature 1.8.1 White .298±.040 .318±.040 1.8.2 Red .627±.040 .369±.040 1.8.3 Green .333±.040 .559±.040 1.8.4 Blue .137±.040 .061±.040 19. Focus 1.9.1 for PROT lens 1.Pattern:区 pattern 2.Observation:2m to screen(wide only) 3.Criteria: 1.pattern uniform and clear-------->OK 2.If can’t focus uniform and clear，switch to 区 pattern and focus uniform clear all over screen (central must clear than corner) Measure flare and defocus a.flare:R,G≦2.5 B≦3.5 b.defocus:≦2.
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DMD Image Specification 1. SCOPE This document specifies the image quality requirements applicable to the XGA RGBW Palmtop Configuration F Component Kit. The Component Kit provides the XGA RGBW Palmtop Projector with Digital Imaging functionality based on Digital Micromirror Device (DMD) technology. 2. Definitions 2.1 Blemish 2.2 A blemish is an obstruction, reflection, or refraction of light that is visible, but out of focus in the projected image under specified conditions of inspection (see Table 1).
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2.9 Border Artifacts All variations of these artifacts are acceptable under this image quality specification. Border artifacts are a general category of image artifacts that may show up on screen in the area outside of the active array. Border artifacts include: Exposed Bond Wires , Exposed Metal 2 , and Reflective Edge. 2.9.1 Bond Wires Bond Wires attach the die to the superstructure. If visible, they will appear as short light parallel lines outside of the Sea of Mirrors ( SOM ). 2.9.
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3. ACCEPTANCE REQUIREMENTS 3.1 Conditions of Acceptance All DMD image quality defects must be determined under the folloeing projected image test conditions : a. Projector degamma shall be linear. b. Projector error diffusion shall be “off “. c. Projector brightness and contrast settings shall be set to nominal. d. The diagonal size of the projected image shall be a minimum of 60 inches. e. The projection screen shall be 1X gain. f. The image shall be in focus during all Table 1 tests. g.
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Projected Image Any screen 1. No adjacent pixels. 2. No bright pixels ( Active Area ) 3. <= 1 bright pixel ( SOM ) 4. ≤ 4 dark pixels 5. ≤ 6 minor blemishes. 6. No DMD window aperture shadowing on the Active Area 7. No unstable pixels in Active Area Notes : 1. Projected blemish numbers include the count for the shadow of the artifact in addition to the artifact itself, so that the count usually represents a single artifact on the window. 2.
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Optical Measurement 1.Scope: This document describes critical optical related test definitions and Instructions for data or video projectors. The other general terminologies are specified in ANSI IT7.228-1997. 2.General Requirements 1. The unit under test should be allowed to stabilize without further adjustment for a minimum of 5 minutes, at nominal ambient room temperature of 25°C, before making measurements. 2.
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L11 L10 L1 L2 L3 L4 L5 L6 L7 L8 L13 L9 L12 Note: L10, L11, L12, L13 are located at 10% of the distance from corner itself to L5 A2. BRIGHTNESS UNIFORMITY Brightness Uniformity = Minimum (L10,L11,L12,L13)/ Average (L1,L2,L3,L4,L5,L6,L7,L8,L9) A3. JBMA UNIFORMITY JBMA Uniformity = Average (L1,L3,L7,L9)/ L5 A4.
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A8. IMAGE DISTORTION Keystone = (W2-W1)/ (W1+W2) x 100% Vertical TV dist = (H1+H2-2xH3)/2H2 x100% Horizontal TV dist = (W1+W2-2xW3)/2W1 x100% W1: image width at image bottom W2: image width at image top W3: image width at the half image height. H1: image height at image left H2: image height at image right H3: image height at half image Note: 1. Keystone and Vertical TV Distortion are recommended for Front Projection Display 2.
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A15. ANSI COLOR UNIFORMITY ANSI Color Uniformity: △u’v’= [(u’1-u’0)^2+(v’1-v’0)^2]^1/2 (u’0,v’0): the average color of L1~L13 (u’1,v’1): the spot with maximum deviation from (u’0,v’0) A16. PROJECTION OFFSET Projection Offset= Image height above projection lens optical axis / Total image height x 100% Note: Optical engine should be kept horizontal attitude A17. Customer Defined Focus i. Focus test procedure (Wide only) a. Pattern: Cross Hatch (Refer to A27 for all related test patterns) b.
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5 4 3 2 1 D D Screw Holes 1 1 5 1 1 GND 9 5 9 5 9 5 4 8 4 8 4 8 4 8 3 7 3 7 3 7 3 7 2 6 2 6 2 6 2 6 H1 H2 HOLE-V8 H3 HOLE-V8 9 POWER H4 HOLE-V8 FAN V12 VDD_F HOLE-V8 C SDA SCL FAN1_E FAN2_B GND V12 V12 V DD_F V DD_F SDA SCL SDA SCL FAN1_E FAN2_B FAN1_E FAN2_B G ND G ND V12 VDD_F C SDA SCL FAN1_E FAN2_B GND Optical Points B OP1 OP OP2 OP OP3 OP OP4 OP OP5 OP OP6 OP OP7 OP OP8 OP OP9 OP OP10 OP OP11 OP OP12 OP OP13 OP OP14
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5 4 3 2 1 RS701 CS701 CS702 47 1000P K 2 9 3 + C7301 470U 25V 2 3 D6301 US1M D7301 10CTQ150S 2 J6302 D6302 18Vcc 2 R6307 1 47 W 1 W DRILL-22 4 D6303 2 SS3H10 CS703 5 + RS703 1 US1J 47 L7301 1 2 R6308 R6309 10KF VDD D7302 ES1D 2060089102 therm 47 47 CS704 10UH C7302 470U 25V R7313 1K D 20D0049108 5 4 3 2 1 R7314 1K + C7305 220U 25V J7302 20L2021005 FAN1_E FAN1_E FAN2_B FAN2_B G1 2200P J 2200P J 47 R7310 2.
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3 2 10M 25.6KHZ 1 NC FR F NC ER E DR D SCL SDA RA501 4.7K R510 VDD_F Q504 2N3904 1 10K R509 CD4049UBCM 10P J 2 10P J 2 2.2K FAN4_P C502 1 C501 Y501 2.4K R508 2.2K + C505 22U RB501 2.2K 16V V12 CA507 0.47U K R517 4.7K U502 14 12 SMBCLK SMBDATA 11 ALERT 6 RESET 1 OUT1 VCC VCC 15 2 DXP1 3 DXN 10 FG1 9 CLK FAN1_B C507 2200P K 5 OUT2 FG2 GND GND 16 13 7 8 C508 2200P K FAN1_P FAN2_B Q505 2N3904 1 R514 10K R516 2.2K VDD_F R515 2.2K G768B 32.
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5 4 3 2 1 D D DMD_CHIP 80*2_CONN DD[63:0] C MBRST[15:0] DCLK_L DMDSER SACCLK SACBUS SCTRL_L LOADB_LZ TRC_L P3P3V VCC2 GND DD[63 :0] MBRST[15:0] DCLK_L D MDSER SACCLK SACBUS SCTRL_L LOADB_LZ TRC_L P3P3V V CC2 G ND DD[63:0] C MBRST[15:0] DCLK_L DMDSER SACCLK SACBUS SCTRL_L LOADB_LZ TRC_L P3P3V VCC2 GND DMD_CHIP 80*2_CONN B B Benq Corporation A Project Code 99.J8677.001 Title 4 3 2 ODM PCB Rev. Document Number S01 99.J8677.
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5 4 3 DD[63 :0] DD[63 :0] 2 1 DD[63:0] J1 D P3P3V TP25 P3P3V SACCLK SACBUS SCTRL_L TRC_L SACCLK SACBUS SCTRL_L TRC_L D D62 D D60 D D58 D D56 D D54 D D52 C D D50 D D48 D D46 D D44 D D42 D D40 D D38 D D36 2 4 6 8 10 12 14 16 18 20 22 24 TP24 26 28 30 TP27 32 TP29 34 TP31 36 TP32 38 40 TP34 42 TP36 44 46 TP38 48 TP40 50 52 TP42 54 TP44 56 58 TP46 60 TP48 62 64 TP50 66 TP52 68 70 TP54 72 TP56 74 76 TP58 78 TP60 80 D 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55
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5 2 TP1 T POINT A TP2 T POINT A D 1 1 E01 E03 E05 G01 C01 G03 D04 G05 C03 H02 A01 H04 D06 H06 D10 K06 B06 K04 B04 L05 C09 L03 C07 A03 A07 D12 B10 A09 B12 C13 A13 A15 U1A D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 MBRST[15:0] DCLK_L LOADB_LZ MBRST_15 MBRST_14 MBRST_13 MBRST_12 MBRST_11 MBRST_10 MBRST_9 MBRST_8 MBRST_7 MBRST_6 MBRST_5 MBRST_4 MBRST_3 MBRST_2 MBRST_1 MBRST_0 DCLK_L C15 DCLK LOADB_LZ B16 LOADB SACCLK SA
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SDA SCL DGE[7:0] DBE[7:0] D HS DVS DCLK D EN POWERON RESETZ LAMPLITZ 3.3V_D SDA0 SCL0 DGE[7:0] DBE[7:0] V12_D DHS DVS VDD_D 3.3V_D DCLK DEN 2V5_D VDD_D 3.3V_D 3 2V5_D V12_D 2V5_D LAMPEN VDD_D PAGE_3 002_DMD 3.3V_D LAMPEN VDD ECO-MODE V DD LAMPEN FAN_P ECO-MODE V12_D POWERON RESETZ LAMPLITZ GND ECO-MODE FAN_P ECO-MODE DBE[7:0] V12_D VDD_D 2V5_D 3.3V_D LAMPEN GND FAN_P SDA SCL 2 ECO-MODE 3.3V VDD VDD 3.3V V DD 3.3V V DD DBE[7:0] DRE[7:0] SCL SDA SCL SDA 3.
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A B C D E Regect RC1 and RC2 before connect DX660 main board with INTERFACE board. SCL SDA VDD V33 CVBS LUMA CVBS GND SDA SCL SDA SCL AVDD AVDD 3 HSYNC HSYNC RAIN_C GAIN_C BAIN_C VSYNC_C HSYNC KEYSTONE ROMWEn ROMOEn VPPEN VPPEN A0 BHENn RESET VVS VFIELD VPEN VHS VCLK ROMOEn VUV[7:0] 3.
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5 4 3 1 DRE[7:0] DRE[7:0] DGE[7:0] DGE[7:0] DBE[7:0] DBE[7:0] DAD1000 V12_D V12_D V12_D 2V5_D 2V5_D 2V5_D VDD_D VDD_D VDD_D VDD 3.3V_D 3.3V_D SR16ADDR0 SR16ADDR1 SR16ADDR2 SR16ADDR3 SR16MODE0 SR16MODE1 3.3V_D SR16SEL0 SR16SEL1 SR16STROBE GND SR16OEZ 3.3V_D 3.
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A B C D J704 3 3 TP242 4 4 5 5 TP244 6 6 7 7 8 8 80 OHM C828 10U M 20V + C824 0.1U K R711 TP243 270 20D0049108 80 OHM L710 80 OHM L711 2V5_D 80 OHM L712 C829 22U 6.3V + C826 0.1U K R784 10K OPEN 4 VDD ECO-MODE 2N3904 VDD_D 80 OHM GND OPEN VDD L713 VDD 1 C827 0.
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A B C D E 4 4 OPEN SCL SCL R16 0 SCL0 3.3V_D SCL0 3.3V_D 3 3 SCL R19 4.7K GND TP14 TP15 TP16 SW1 2240138001 J2 3 2 1 20L2021003 1 2 3 1 2 3 4 5 6 4 5 6 R18 4.7K SAD OPEN SDA SDA R21 0 SDA0 SDA0 SW1 is the switch to choice DDP1000 I2C would be connected with Pixelwork I2C or not. J2 is the connector to DDP1000 I2C download by DDP1000 composer. 2 2 Benq Corporation Project Code 99.J8677.001 1 Title Model Name OEM/ODM Model Name PB6100 Size PCB P/N 48.
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A B C VDD 2 2 2 DG1 3 3 3 BAV99 G2 PC-TXD RG9 1 TZMC5V1 1 TZMC5V1 2 DG713 2 DG712 TP229 3 1 1 VDD PC-TXD 1 DG9 1 DG10 2 150P J 1N4148 DDC5V_2 CG3 2 1N4148 4.7K RG6 75 4.7K RG7 75 RG10 4.7K 2 TZMC5V1 RG11 CG2 4.7K 2 TZMC5V1 470P K U9 5 SDA GND 4 6 SCL A2 3 7 WP A1 2 8 VCC A0 1 R842 RG21 0 RAIN_C RG22 0 GAIN_C RG23 RG3 RG4 RG5 0 75 75 75 BAIN_C RAIN_C GAIN_C BAIN_C VDD 0.1U 4.7K 5 15 4 2 1N4148 CG1 2 UH2 R795 0 HSYNC 4 74AHCT1G14 HSYNC 73.07414.
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A B V33 R60 4.7K R61 4.7K D E DECOE SCL SDA CA53 CA54 CA55 CA56 CA57 CA58 CA59 CA60 C300 C301 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 25V Z AVDD AVDD 4 1 CA20 10K 4 LD1117-3.3V VOUT 2 VIN VO 4 CA19 22U 25V + 2 VO UA6 3 0.
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A B C D E AVDD AVDD_AD OPEN AVDD AVDD V33 PVDD AVDD_AD 0 R860 1 PVDD V33 3900P K 39N K REF_A 0.1U 22U 25V 0.1U 0.1U 0.1U 0.1U PVDD For Batman DVD noise solution 2 0.1U GVMID AVDD_AD V33 VIN C62 LD1117-3.3V VOUT 2 VO 4 PVDD PVDD 1 AVDD_AD VSYNC_C R47 47 GCOAST GBLKSPL C61 C835 10U 16V + 0.1U 2 VSYNC_C HSYNC GCOAST GBLKSPL C56 0.1U GND CD1 10P J 3 VDD GFILT 3.3K OPEN C55 0.1U UB16 SOGIN RD2 3K C54 0.1U GND VDD 1.5K C53 0.1U 4 80 OHM 68.00173.
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A B C D E OPEN U17 A[19:1] A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 FCEn VCC 37 3.3V D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 29 31 33 35 38 40 42 44 30 32 34 36 39 41 43 45 GND GND 46 27 R86 3 2N3906 C90 C305 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 0.1U R87 1K ROMOEn ROMWEn 3.3V ROMOEn ROMWEn R99 3.3K R98 3.
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A B C GFBK GGE0 GGE1 GGE2 GGE3 GGE4 GGE5 GGE6 GGE7 GBE0 GBE1 GBE2 GBE3 GBE4 GBE5 GBE6 GBE7 D16 A18 C17 B18 A19 B19 A20 D18 GBE0 GBE1 GBE2 GBE3 GBE4 GBE5 GBE6 GBE7 K20 L17 L18 L19 L20 M18 M17 M19 GRO0 GRO1 GRO2 GRO3 GRO4 GRO5 GRO6 GRO7 E17 C19 B20 C20 E18 F17 D19 D20 GGO0 GGO1 GGO2 GGO3 GGO4 GGO5 GGO6 GGO7 SDA SCL AUDIO_VOL AUDIO_MUT LAMPLITZ CONTROL VPPEN U22A D12 VCLK VPEN C13 VPEN VVS VHS VFIELD VY[7:0] A14 B14 A15 VVS VHS VFIELD Graphics Port V Y0 V Y1 V Y2 V Y3 V Y4 V Y5 V Y6 V Y7
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A B C D E 3.3V 4 3.3V 3.3V 3.3V POWERON POWERON Y3 7 U25_X1 U25_X2 OE VDD 2 6 4 S0 S1 CLK 5 1 8 X1 X2 GND 3 16.257MHZ RD CK R113 22 DCKEXT 65MHz DCKEXT Y2 16.257MHZ C126 10P D 10P D OE VDD 2 6 4 S0 S1 CLK 5 1 8 X1 X2 GND 3 RMCK R112 L28 MCKEXT 22 130MHz/41MHz MCKEXT Z10 68.00129.0D1 ICS501 R114 L29 Z10 GND C123 10P D 68.00129.0D1 820K C125 U24_X1 U24_X2 7 820K ICS501 R115 U24 C122 0.1U U25 4 C121 0.1U C124 10P D 3 3 OPEN 3.
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A B C D E VDD VDD 0 R858 0 3 2 1 R15 VDD 47 IRV CC IROUT R23 510 IRRCVR1 C12 TP48 TP49 C815 L802 240 OHM R857 470P K C816 VS GND OUT VDD R22 10K 240 OHM L801 J813 1 2 3 4 20L2021004 470P K VDD R813 4.
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A B C D E 2V5_D 4 DDP1000 BULK DECOUPLING CAPS DDP1000 DECOUPLING FOR +3.3V 3.3V_D 1 C136 10U M 6.3V + 2 2 + 3.3V_D 2V5_D 4 2V5_D 2V5_D 2V5_D 2V5_D 2V5_D 2V5_D 3.3V_D 1 3.3V_D C128 0.1U C137 10U M 6.3V C129 0.1U 3.3V_D C130 0.1U 3.3V_D C138 0.1U 2V5_D C139 0.1U C140 0.1U C131 0.1U C132 0.1U 2V5_D C133 0.1U 2V5_D C141 0.1U 2V5_D C142 0.1U C143 0.1U C134 0.1U 2V5_D C144 0.1U C135 0.1U 2V5_D C145 0.1U 2V5_D 1 3.3V_D 2 + C146 10U M 6.3V 3.3V_D C147 0.
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A B C D E FLDATA[0:15] U29A U30 4 FLDATA0 FLDATA1 FLDATA2 FLDATA3 FLDATA4 FLDATA5 FLDATA6 FLDATA7 FLDATA8 FLDATA9 FLDATA10 FLDATA11 FLDATA12 FLDATA13 FLDATA14 FLDATA15 AE23 AE22 AC21 AF23 AE21 AD21 AC20 AF22 AE20 AD20 AF20 AD19 AC18 AE18 AF19 AD18 FLDATA0 FLDATA1 FLDATA2 FLDATA3 FLDATA4 FLDATA5 FLDATA6 FLDATA7 FLDATA8 FLDATA9 FLDATA10 FLDATA11 FLDATA12 FLDATA13 FLDATA14 FLDATA15 FLASH INTERFACE FLADDR19 FLADDR18 FLADDR17 FLADDR16 FLADDR15 FLADDR14 FLADDR13 FLADDR12 FLADDR11 FLADDR10 FLADDR9 FLAD
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A B C D E 4 4 US2 3.3V_D UY1 3.3V_D 7 OE 6 4 S0 S1 1 8 Y5 20MHZ RY1 CLK GND L16 2 120 OHM CK100M R136 5 3 L27 3.3V_D 39.2F MOSC 1 A 2 B 3 GND MOSC 5 Y 4 CWINDEX CWINDEX 74AHC1G32 C493 22P J Z10 VDD_D VCC 68.00129.0D1 ICS501 820K C166 10P J X1 X2 VDD CWINDEXA CWINDEXA C167 10P J 3 3 3P3V R518 open 0 VDD_D TP55 CWSENSOR OPDIODE VDD_D RS5 180 RS6 75K JS1 3 2 1 R920 TP53 TP54 3.3V_D 0 R927 3P3V C921 0.1U C909 20L2021003 0 RS7 2K 4.
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A B C VTERM C171 150U 6.3V 2 R139 R140 10K 10K 4 5 6 7 8 VTERM + R138 10K E 2V5_D 1 VDRCG D C172 0.1U C173 0.1U C174 0.1U C175 0.1U VDRCG RN31 39 4 3 2 1RN33 39 5 4 6 3 7 2 8 1 DQB1 RQ3 RQ2 RQ6 RQ0 RQ1 RQ4 RQ7 RDRAM VDD DECOUPLING CAPS 2 7 6 REFCLK SYNCLKN PCLKM CLK VDD VDD MULT0 VDD MULT1 VDD NC GND:4,5,8,17,21 S0 VDRCG:3,9,16,22 S1 NC:19 S2 GND PWRDNB GND STOPB GND GND VDDIR GND MULT0 15 MULT1 14 DRCGPDZ 24 23 13 2V5_D 12 11 STOPZ 10K R143 1 2V5_D 10 3 C178 0.
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A B C D E DD[0:63] U29C DD[0:63] ADD[63:0] DD63 DD62 DD61 DD60 DD59 DD58 DD57 DD56 DD55 DD54 DD53 DD52 DD51 DD50 DD49 DD48 DD47 DD46 DD45 DD44 DD43 DD42 DD41 DD40 DD39 DD38 DD37 DD36 DD35 DD34 DD33 DD32 DD31 DD30 DD29 DD28 DD27 DD26 DD25 DD24 DD23 DD22 DD21 DD20 DD19 DD18 DD17 DD16 DD15 DD14 DD13 DD12 DD11 DD10 DD9 DD8 DD7 DD6 DD5 DD4 DD3 DD2 DD1 DD0 4 A25 D0 D22 D1 DGE[7:0] DGE[7:0] DGE7 DGE6 DGE5 DGE4 DGE3 DGE2 DGE1 DGE0 3 F24 F25 D26 F23 E25 D25 C26 E24 D24 C25 A9 A8 A7 A6 A5 A4 A3 A2 A1
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A B C 4 D E 4 The width of net MBRST[0:15] should be larger than 11mils and the distance between two net should be larger than 11 mils. 3.3V_D 3.3V_D TP217 R253 1K TP220 TP218 TP219 MBRST[0:15] TP221 MBRST[0:15] U701 0 open open V12_D L703 P12V_FLT 120 OHM C712 0.1U Z C711 0.1U Z C710 0.1U Z C709 0.1U Z C708 4.7U Z 1 VBIAS C714 0.1U Z + 2 C715 0.1U Z C713 3.
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A B V12_D D E L19 4 C234 0.1U M C235 0.1U M GND L20 DN11 BAT54SW 2 2 3 DN12 BAT54SW ALVDD 3 DN13 BAT54SW 3 1 VDD_D VDD_D 3 1 DN14 BAT54SW 1 C233 0.1U M C231 22U 25V 1 C232 0.1U M + 2 80 OHM 2 1 V12_D 2 4 C 80 OHM C236 0.1U K U41 1 ALVDD R198 R199 R200 R201 R202 C237 0.
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A B C D E DD[0:63] DD[0:63] JP2 DD62 DD60 DD58 DD56 DD54 DD52 DD50 DD48 3 DD46 DD44 DD42 DD40 DD38 DD36 DD34 DD32 DD30 DD28 DD26 DD24 DD22 DD20 2 DD18 DD16 DD14 DD12 DD10 D D8 D D6 D D4 D D2 D D0 GND MBRST14 MBRST12 MBRST10 MBRST8 MBRST6 MBRST4 MBRST2 MBRST0 1 20L1066080 JP3 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 Screw Holes 4 BINSEL0 BINSEL1 VCC2 VCC2 DMDSER LOADB-LZ DCLK-L DMDSER LOADB-LZ 5 1 2 4 6 8 10 12 14