Specifications

Operation Manual
EL640.400-C2, -C3 and -
CD3 Display
Beneq Products Oy
Olarinluoma 9
Tel. [phone]
VAT ID FI25115461
FI-02200 Espoo
Fax [phone]
www.beneq.com
Finland
[e-mail]
www.lumineq.com
Date: September 23, 2014
Document number: ED000821B
Page | 5
3.2 Input to the display
Table 1. Input to the display
Pins
Signal
Symbol
Description
J1(Data/power input connector)
1, 2
Voltage
V
cc2
Supply voltage (+11 V …+30 V) converted to
required internal high voltages (see J2).
3, 4
Voltage
V
cc1
Supply voltage (+5 V) for the logic (see J2).
5
Blanking
_BLANK
Used in VGA and SPECIAL modes. In NORMAL
mode, should be high or left disconnected.
6,8,10
12,14,16
Ground
GND
Signal return.
7
Two-bit
data
TVID
Second data input for two-bits-parallel mode. The
TVID input is for odd columns and the VID for
even ones.
9
Vertical
Sync
VS
The vertical sync signal VS controls the vertical
position of the picture.
11
Horizontal
Sync
HS
The horizontal sync signal HS controls the
internal row counter and in the NORMAL mode
the horizontal position of the picture.
13
Video Clock
VCLK
The VCLK signal shifts data present on the VID
and TVID lines into the display system. VCLK is
active on the rising edge.
15
Video Data
VID
Signal that supplies the pixel information to the
system.
J2 (Optional power input connector)
1
Voltage
V
cc2
Same as J1, Pins 1, 2 (not necessary to connect if
power is supplied via J1).
2, 3
Ground
GND
Same as J1 Pins 6, 8, 10, 12, 14, 16 (not
necessary to connect if power is supplied via J1).
4
Voltage
V
cc1
Same as J1 Pins 3, 4 (not necessary to connect if
power is supplied via J1).