User Manual

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© 2014 Premier Farnell plc. All Rights Reserved
6.12.3 PRU-ICSS Pin Access
Both PRU 0 and PRU1 are accessible from the expansion headers. Some may not be
useable without first disabling functions on the board like LCD for example. Listed below is
what ports can be accessed on each PRU.
PRU0
• 8 outputs or 9 inputs
PRU1
• 13 outputs or 14 inputs
•
UART0_TXD, UART0_RXD, UART0_CTS, UART0_RTS
Table 10 below shows which PRU-ICSS signals can be accessed on the element14
BeagleBone Black and on which connector and pins they are accessible from. Some
signals are accessible on the same pins.
Table 10 PRU0 and PRU1 Access
P
I
N
P
R
OC
N
A
ME
P8
11
R12
GPI
O
1
_
1
3
p
r
1_
p
ru
0_
p
ru
_
r
30_15
(
O
u
tp
u
t
)
12
T
1
2
GPI
O
1
_
1
2
pr1_pru0_pru_r30_14 (Output)
15
U13
GPI
O
1
_
1
5
pr1_pru0_pru_r31_15 (Input)
16
V
1
3
GPI
O
1
_
1
4
pr1_pru0_pru_r31_14 (Input)
20
V9
GPI
O
1
_
3
1
pr1_pru1_pru_r30_13 (Output) pr1_pru1_pru_r31_13 (INPUT)
21
U9
GPI
O
1
_
3
0
pr1_pru1_pru_r30_12 (Output) pr1_pru1_pru_r31_12 (INPUT)
27
U5
GPI
O
2
_
2
2
pr1_pru1_pru_r30_8 (Output) pr1_pru1_pru_r31_8 (INPUT)
28
V5
GPI
O
2
_
2
4
pr1_pru1_pru_r30_10 (Output) pr1_pru1_pru_r31_10 (INPUT)
29 R5 GPIO2_23
p
r
1_p
r
u1_
p
r
u_
r
3
0_9
(
O
u
t
p
u
t
)
p
r
1_p
r
u1_
p
r
u_
r
3
1_9
(
IN
P
U
T
)
39
T3
GPI
O
2
_
1
2
pr1_pru1_pru_r30_6 (Output) pr1_pru1_pru_r31_6 (INPUT)
40
T4
GPI
O
2
_
1
3
p
r
1_p
r
u1_
p
r
u_
r
3
0_7
(
O
u
t
p
u
t
)
p
r
1_p
r
u1_
p
r
u_
r
3
1_7
(
IN
P
U
T
)
41
T1
GPI
O
2
_
1
0
pr1_pru1_pru_r30_4 (Output) pr1_pru1_pru_r31_4 (INPUT)
42
T2
GPI
O
2
_
1
1
pr1_pru1_pru_r30_5 (Output) pr1_pru1_pru_r31_5 (INPUT)
43
R3
GPI
O
2
_
8
pr1_pru1_pru_r30_2 (Output) pr1_pru1_pru_r31_2 (INPUT)
44
R4
GPI
O
2
_
9
pr1_pru1_pru_r30_3 (Output) pr1_pru1_pru_r31_3 (INPUT)
45
R1
GPI
O
2
_
6
pr1_pru1_pru_r30_0 (Output) pr1_pru1_pru_r31_0 (INPUT)
46
R2
GPI
O
2
_
7
pr1_pru1_pru_r30_1 (Output) pr1_pru1_pru_r31_1 (INPUT)
P9
17 A16 I2C1_SCL
pr1_uart0_txd
18 B16 I2C1_SDA
pr1_uart0_rxd
19
D
1
7
I2
C2
_
SC
L
pr1_uart0_rts_n
20
D
1
8
I2
C2
_
S
D
A
pr1_uart0_cts_n
21
B
1
7
U
A
R
T
2
_
TX
D
pr1_uart0_rts_n
22
A
1
7
U
A
R
T
2
_
R
X
D
pr1_uart0_cts_n
24
D
1
5
U
A
R
T
1
_
TX
D
pr1_uart0_txd
pr1_pru0_pru_r31_16 (Input)
25
A
1
4
G
P
I
O
3
_
2
1*
pr1_pru0_pru_r30_5
(
O
u
tp
u
t
)
pr1_pru0_pru_r31_5((Input
)
26
D
1
6
U
A
R
T
1
_
R
X
D
pr1_uart0_rxd pr1_pru1_pru_r31_16
27 C13 GPIO3_19
pr1_pru0_pru_r30_7 (Output) pr1_pru0_pru_r31_7 (Input)
28
C
1
2
SP
I1
_
C
S
0
eC
A
P
2_
in
_
P
W
M2_
o
u
t
pr1_pru0_pru_r30_3 (Output) pr1_pru0_pru_r31_3 (Input)
29
B
1
3
SP
I1
_
D
0
pr1_pru0_pru_r30_1 (Output) pr1_pru0_pru_r31_1 (Input)
30
D
1
2
SP
I1
_
D
1
pr1_pru0_pru_r30_2 (Output) pr1_pru0_pru_r31_2 (Input)
31
A
1
3
SP
I1_
S
CL
K
pr1_pru0_pru_r30_0 (Output) pr1_pru0_pru_r31_0 (Input)