User Manual

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6.12 PRU-ICSS
The PRU-ICSS module is located inside the AM3358 processor. Access to these pins is
provided by the expansion headers and is multiplexed with other functions on the board.
Access is not provided to all of the available pins.
All documentation is located at http://github.com/beagleboard/am335x_pru_package. This
feature is not supported by Texas Instruments.
6.12.1 PRU-ICSS Features
The features of the PRU-ICSS include:
Two independent programmable real-time (PRU) cores:
– 32-Bit Load/Store RISC architecture
– 8K Byte instruction RAM (2K instructions) per core
– 8K Bytes data RAM per core
– 12K Bytes shared RAM
• Operating frequency of 200 MHz
• PRU operation is little endian similar to ARM processor
• All memories within PRU-ICSS support parity
• Includes Interrupt Controller for system event handling
• Fast I/O interface
– 16 input pins and 16 output pins per PRU core. (Not all of these are accessible on the
element14 BeagleBone Black).
6.12.2 PRU-ICSS Block Diagram
Figure 49 is a high level block diagram of the PRU-ICSS.
Figure 49 PRU-ICSS Block Diagram