User Manual

element14 is a trademark of Premier Farnell plc 65

6.9.3 Ethernet PHY Power, Reset, and Clocks

Figure 42

shows the power, reset, and lock connections to the

LAN8710A

PHY. Each of

these areas is discussed in more detail in the following sections.

Figure 42 Ethernet. PHY, Power, Reset and Clocks

6.9.3.1 VDD_3V3B Rail

The VDD_3V3B rail is the main power rail for the

LAN8710A

. It originates at the VD_3V3B

regulator and is the primary rail that supports all of the peripherals on the board. This rail

also supplies the VDDIO rails which set the voltage levels for all of the I/O signals between

the processor and the

LAN8710A

6.9.3.2 VDD_PHYA Rail

A filtered version of VDD_3V3B rail is connected to the VDD rails of the LAN8710 and the

termination resistors on the Ethernet signals. It is labeled as

VDD_PHYA

. The filtering

inductor helps block transients that may be seen on the VDD_3V3B rail.