User Manual
element14 is a trademark of Premier Farnell plc 55
© 2014 Premier Farnell plc. All Rights Reserved
6.2.8 Power Rails
The
DDR3L
memory device and the DDR3 rails on the processor are supplied by the
TPS65217C
. Default voltage is 1.5V but can be scaled down to 1.35V if desired.
6.2.9 VREF
The
VREF
signal is generated from a voltage divider on the
VDDS_DDR
rail that
powers the processor DDR rail and the DDR3L device itself.
Figure 33
below shows the
configuration of this signal and the connection to the DDR3L memory device and the
processor.
Figure 33 DDR3L VREF Design