User Manual

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6.2.7 DDR3L Memory Design

Figure 32

is the schematic for the DDR3L memory device. Each of the groups of signals

is described in the following lines.

Address Lines:

Provide the row address for ACTIVATE commands, and the column

address and auto pre-charge bit (A10) for READ/WRITE commands, to select one location

out of the memory array in the respective bank. A10 sampled during a PRECHARGE

command determines whether the PRECHARGE applies to one bank (A10 LOW,

bank selected by BA[2:0]) or all banks (A10 HIGH). The address inputs also provide the

op-code during a LOAD MODE command. Address inputs are referenced to VREFCA.

A12/BC#: When enabled in the mode register (MR), A12 is sampled during READ and

WRITE commands to determine whether burst chop (on-the-fly) will be performed (HIGH =

BL8 or no burst chop, LOW = BC4 burst chop).

Bank Address Lines:

BA[2:0] define the bank to which an ACTIVATE, READ, WRITE, or

PRECHARGE command is being applied. BA[2:0] define which mode register (MR0,

MR1, MR2, or MR3) is loaded during the LOAD MODE command. BA[2:0] are referenced

to V

REFCA

CK and CK# Lines:

are differential clock inputs. All address and control input signals are

sampled on the crossing of the positive edge of CK and the negative edge of CK#. Output

data strobe (DQS, DQS#) is referenced to the crossings of CK and CK#.

Clock Enable Line:

CKE enables (registered HIGH) and disables (registered LOW)

internal circuitry and clocks on the DRAM. The specific circuitry that is enabled/disabled is

dependent upon the DDR3 SDRAM configuration and operating mode. Taking CKE LOW

provides PRECHARGE power-down and SELF REFRESH operations (all banks idle) or

active power-down (row active in any bank). CKE is synchronous for power- down

entry and exit and for self refresh entry. CKE is asynchronous for self refresh exit. Input

buffers (excluding CK, CK#, CKE, RESET#, and ODT) are disabled during power- down.

Input buffers (excluding CKE and RESET#) are disabled during SELF REFRESH. CKE is

referenced to V

REFCA