Data Sheet

AM3359, AM3358, AM3357
AM3356, AM3354, AM3352
www.ti.com
SPRS717F OCTOBER 2011REVISED APRIL 2013
1-Bit, 4-Bit and 8-Bit MMC, SD, and SDIO a Firmware Timer
Modes
512-Word Deep Internal FIFO
MMCSD0 has dedicated Power Rail for
Supported Display Types:
1.8-V or 3.3-V Operation
Character Displays - Uses LCD
Up to 48-MHz Data Transfer Rate
Interface Display Driver (LIDD)
Supports Card Detect and Write Protect Controller to Program these Displays
Complies with MMC4.3 and SD and SDIO Passive Matrix LCD Displays - Uses
2.0 Specifications LCD Raster Display Controller to
Provide Timing and Data for Constant
Up to Three I2C Master and Slave Interfaces
Graphics Refresh to a Passive Display
Standard Mode (up to 100 kHz)
Active Matrix LCD Displays - Uses
Fast Mode (up to 400 kHz)
External Frame Buffer Space and the
Up to Four Banks of General-Purpose IO
Internal DMA Engine to Drive
(GPIO)
Streaming Data to the Panel
32 GPIOs per Bank (Multiplexed with
12-Bit Successive Approximation Register
Other Functional Pins)
(SAR) ADC
GPIOs Can be Used as Interrupt Inputs
200K Samples per Second
(Up to Two Interrupt Inputs per Bank)
Input Can be Selected from any of the
Up to Three External DMA Event Inputs That
Eight Analog Inputs Multiplexed Through
Can Also be Used as Interrupt Inputs
an 8:1 analog Switch
Eight 32-Bit General-Purpose Timers
Can be Configured to Operate as a 4-wire,
DMTIMER1 is a 1-ms Timer Used for
5-wire, or 8-wire Resistive Touch Screen
Operating System (OS) Ticks
Controller (TSC) Interface
DMTIMER4 - DMTIMER7 are Pinned Out
Up to Three 32-Bit Enhanced Capture
One Watchdog Timer
Modules (eCAP)
SGX530 3D Graphics Engine
Configurable as Three Capture Inputs or
Tile-Based Architecture Delivering Up to
Three Auxiliary PWM Outputs
20 Million Polygons per second
Up to Three Enhanced High-Resolution PWM
Universal Scalable Shader Engine is a
Modules (eHRPWM)
Multi-Threaded Engine Incorporating
Dedicated 16-Bit Time-Base Counter with
Pixel and Vertex Shader Functionality
Time and Frequency Controls
Advanced Shader Feature Set in Excess
Configurable as Six Single-Ended, Six
of Microsoft VS3.0, PS3.0 and OGL2.0
Dual-Edge Symmetric, or Three Dual-
Industry Standard API Support of
Edge Asymmetric Outputs
Direct3D Mobile, OGL-ES 1.1 and 2.0,
Up to Three 32-Bit Enhanced Quadrature
OpenVG 1.0, and OpenMax
Encoder Pulse (eQEP) Modules
Fine-Grained Task Switching, Load
Device Identification
Balancing and Power Management
Contains Electrical fuse Farm (FuseFarm) of
Advanced Geometry DMA Driven
Which Some Bits are Factory Programmable
Operation for Minimum CPU Interaction
Production ID
Programmable High-Quality Image Anti-
Device Part Number (Unique JTAG ID)
Aliasing
Device Revision (readable by Host ARM)
Fully Virtualized Memory Addressing for
Debug Interface Support
OS Operation in a Unified Memory
JTAG and cJTAG for ARM (Cortex-A8 and
Architecture
PRCM), PRU-ICSS Debug
LCD Controller
Supports Device Boundary Scan
Up to 24-Bits Data Output; 8-Bits per
Supports IEEE 1500
Pixel (RGB)
DMA
Resolution Up to 2048x2048 (With
On-Chip Enhanced DMA Controller (EDMA)
Maximum 126-MHz Pixel Clock)
has Three Third-Party Transfer Controllers
Integrated LCD Interface Display Driver
(TPTC) and One Third-Party Channel
(LIDD) Controller
Controller (TPCC), Which Supports Up to 64
Integrated Raster Controller
Programmable Logical Channels and Eight
Integrated DMA Engine to Pull Data from
QDMA Channels. EDMA is Used for:
the External Frame Buffer without
Transfers to and from On-Chip Memories
Burdening the Processor via Interrupts or
Copyright © 2011–2013, Texas Instruments Incorporated Device Summary 3
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