Data Sheet

SPI_CS[x] (Out)
SPI_SCLK (Out)
SPI_SCLK (Out)
SPI_D[x] (SOMI, In)
Bit n-1 Bit n-2
Bit n-3
Bit n-4
Bit 0
PHA=0
EPOL=1
POL=0
POL=1
8 9
3
4
2
1
2
3
5
SPI_CS[x] (Out)
SPI_SCLK (Out)
SPI_SCLK (Out)
SPI_D[x] (SOMI, In)
Bit n-1 Bit n-2
Bit n-3
Bit 1
Bit 0
PHA=1
EPOL=1
POL=0
POL=1
8 9
3
2
1
2
3
1
4
5
4
5 5
4
1
AM3359, AM3358, AM3357
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SPRS717F OCTOBER 2011REVISED APRIL 2013
Case P > 20.8 ns, A = (TCS+0.5)*Fratio*TSPICLKREF (TCS is a bit field of MCSPI_CH(i)CONF register).
Note: P = SPI_CLK clock period.
(5) B = (TCS+0.5)*TSPICLKREF*Fratio (TCS is a bit field of MCSPI_CH(i)CONF register, Fratio: Even2).
Figure 5-90. SPI Master Mode Receive Timing
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