User`s manual

35
DRAM Timing
When “By SPD” has been select, BIOS will read SDRAM module SPD information pre-define by
memory module manufacture.
SDRAM CAS Latency
When synchronous DRAM is installed, the number of clock cycles of CAS latency depends on the
DRAM timing. The settings are: 2T and 2.5T.
Note: Change these settings only if you are familiar with the chipset.
SDRAM RAS# to CAS# Delay
This field let’s you insert a timing delay between the CAS and RAS strobe signals, used when
DRAM is written to, read from, or refreshed.
Fast
gives faster performance; and
Slow
gives more
stable performance. This field applies only when synchronous DRAM is installed in the system.
The settings are: 2T, 3T and 4T.
SDRAM RAS# Precharge Time
If an insufficient number of cycles is allowed for the RAS to accumulate its charge before
DRAM refresh, the refresh may be incomplete and the DRAM may fail to retain date.
Fast gives faster performance; and Slow gives more stable performance. This field
applies only when synchronous DRAM is installed in the system. The settings are: 2T, 3T
and 4T.
3-6-2 AGP & P2P Bridge Control Settings
Phoenix – AwardBIOS CMOS Setup Utility
AGP 7 P2P Bridge Control
Item Help
AGP Aperture Size [64M]
AGP Driving Control [Auto]
X AGP Driving Value DA
AGP Fast Write [Disabled]
AGP Master 1 WS Write [Disabled]
AGP Master 1 WS Read [Disabeld]
Menu Level >>
↑↓→←
Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5:Previous Values F6:Optimized Defaults F7:Standard Defaults
AGP Aperture Size
This function determines the amount of system memory that is given to the AGP. Options
available range from 4MB to 256MB. This is a dynamic memory allotment in the AGP video will
only use the amount of memory that it needs. The remaining memory not in use will be available
for the system to use.
AGP Driving Control