User`s manual

32
3-6 Advanced Chipset Features
Phoenix – AwardBIOS CMOS Setup Utility
Advanced Chipset Features
Item Help
DRAM Timing Selectable [By SPD]
x DRAM RAS# to CAS# Delay Auto
x DRAM RAS# Precharge Auto
x Precharge delay (tRAS) Auto
x System Memory Frequency Auto
System BIOS Cacheable [Enabled]
Video BIOS Cacheable [Disabled]
AMT BIOS Support [Disabled]
** VGA Setting **
PEG/Onchip VGA Control [Auto]
On-Chip Frame Buffer Size [ 8MB]
DVMT Mode [DVMT]
DVMT/FIXED Memory Size [ 128MB]
Menu Level >
↑↓→←
Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5:Previous Values F6: Fail-Safe Defaults F7: Optimized Defaults
DRAM Timing Selectable
Control the DRAM timing manually by the SPD (EEPROM on the RAM
module).
DRAM RAS# To CAS# Delay
This field allow you to insert a timing delay between the CAS and RAS strobe.
Avalable choices: 2 or 3.
DRAM RAS# Precharge
Select the number of CPU clocks allocated for the RAS# signal to accumulate its
charge before the DRAM is refreshed. Available choice : 2 or 3.
Precharge delay (tRAS)
Select the delay between active and precharge command.
System Memory Frequency
Sets the frequency of the RAM module.