User`s manual

3-6-1 Advanced DRAM Control

Advanced DRAM Control

Item Help

Auto Configuration Optimized

Precharge Command 3T

Active Command 5T

Active to CMD Command 2T

Write Recovery Time 2T

SDRAM Cycle Length By SPD

Bank Interleave By SPD

DRAM Drive Strength Auto

x DRAM Drive Value 21

PCI Master Pipeline Req Disabled

P2C/C2P Concurrency Disabled

Fast R-W Turn Around Disabled

CPU to PCI Post Write Enabled

PCI Dynamic Bursting Disabled

PCI Master 0 WS Write Disabled

PCI Delay Transaction Enabled

PCI#2 Access #1 Retry Disabled

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Precharge Command

If an insufficient number of cycles is allowed for the RAS to accumulate its charge before

DRAM refresh, the refresh may be incomplete and the DRAM may fail to retain date. Fast

gives faster performance; and Slow gives more stable performance. This field applies only

when synchronous DRAM is installed in the system. The settings are: 2 and 3.

Active Command

This field let’s you insert a timing delay between the CAS and RAS strobe signals, used when

DRAM is written to, read from, or refreshed. Fast gives faster performance; and Slow gives

more stable performance. This field applies only when synchronous DRAM is installed in the

system. The settings are: 2 and 3.

Active to CMD Command

Select the number of SCLKs for an access cycle. The settings are: 5/7 and 6/8.

SDRAM Cycle Length

When synchronous DRAM is installed, the number of clock cycles of CAS latency depends on

the DRAM timing. The settings are: 2 and 3.

PCI Delay Transaction

The chipset has an embedded 32-bit posted write buffer to support delay transactions cycles.

Select Enabled to support compliance with PCI specification version 2.1. The settings are:

Enabled and Disabled.