Service manual

ABCDE F
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HIJKLMN
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~ N Board Schematic Diagram [ Digital I/F ] Page 2/7 ~
+3V3D
RDATA[0-15]
ATX
NAND_ALE,NAND_CLE,NAND_RBB
+3V3D
FOEB
FCSB1
FWEB
nNAND_WP
48 43
65
46
4321
47 45 44
42 41
3738
3940
12
10
11
987
36
313233
3435
181716
151413
30 29 28 27 26
25
242322212019
IC3206
NC
NC
NC
NC
NC
GND
RB
FOE
CE
NC
NC
VCC
VSS
NC
NC
CLE
ALE
WE
WP
NC
NC
NC
NC
NC NC
NC
NC
NC
I/O1
I/O2
IO/3
IO/4
NC
NC
NC
VSS
VCC
NC
NC
NC
IO/5
IO/6
IO/7
IO/8
NC
NC
NC
NC
+3V3D_STRAPS
68
RB3209
1
2
3
4
5
6
7
8
DQ[0-15]
68
RB3203
1
2
3
4
5
6
7
8
100RB3201
1
2
3
4
5
6
7
8
+2V5D_DDR
DBA0,DBA1,DCASB,DCLK,DCLKB,DCSB,DQM0,DQM1,DQS0,DQS1,DRASB,DVREF,DWEB
68
RB3204
1
2
3
4
5
6
7
8
68
RB3208
1
2
3
4
5
6
7
8
100
RB3206
1
2
3
4
5
6
7
8
100
RB3202
1
2
3
4
5
6
7
8
100
RB3207
1
2
3
4
5
6
7
8
DADD[0-12]
6.3V
100
C3212
PWMOUT
+3V3D
CLK27M
27MHz
X3200
0uH
FB3200
0uH
FB3201
100
RB3200
1
2
3
4
5
6
7
8
48
9
5356
1
495051
2
55 54 52
345678
47
10
46 45 44
43 42
11 12 13 14 15
41 40 39 38 37 36 35
16 17 18 19 20 21
22
34 33
23
24 3225 31302926 27 28
5758
59606162
63
646566
IC3200
EDD1216AATA-6B-E
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
VDDQ
LDQS
NC
VDD
NC
LDM
WE
CAS
RAS
CS
NC
BS0
BS1
A10
A0
A1
A2
A3
DQ15
VSS
A4
A5
A6
A7
A8
A9
A11
A12
NC
CKE
CLK
CLK
UDM
VSS
VREF
NC
UDQS
VSSQ
NC
DQ8
VDDQ
DQ9
DQ10
VSSQ
DQ11
DQ12
VDDQ
DQ13
DQ14
VSSQ
VSS
VDD
8765
4321
KA5SDKASO1TSL
IC3201
X1
NC
VIN
GND
REFOUT
Vcc
NC
X2
1k
R3238
XX
R3217
2.2k
R3212
1k
R3262
1k
R3224
10V
4.7
C3201
XX
R3233
2.2k
R3214
0.001
C3230
10V
4.7
C3211
470
R3251
100
R3203
0.1
C3219
1k
R3236
XX
R3215
1k
R3218
2.2k
R3220
0.1
C3207
0.1
C3210
2.2k
R3213
68
R3240
68
R3202
1k
R3206
1/16W
RN-CP
100
R3200
100
R3204
1/16W
100
R3201
10k
R3239
XX
R3208
XX
R3207
XX
R3235
2.2k
R3211
0.1
C3203
1k
R3227
1/16W
47
R3205
XX
R3226
10V
0.1
C3200
XX
R3221
XX
R3219
0.1
C3202
10V
4.7
C3217
10V
0.1
C3216
50V
0.001
C3215
1k
R3234
0.1
C3220
XX
R3209
100
R3242
XX
R3210
0.1
C3218
10V
XX
R3231
10V
0.1
C3214
1k
R3230
XX
R3263
10V
0.1C3208
1k
R3216
10V
0.1
C3209
10V
0.1
C3205
1k
R3232
XX
R3223
1k
R3229
1k
R3222
XX
R3225
XX
R3228
10V
1
C3206
XX
R3237
6p
C3204
6p
C3213
RDATA[10]
RDATA[2]
RDATA[5]
RDATA[4]
RDATA[12]
RDATA[15]
RDATA[13]
RDATA[0]
RDATA[1]
RDATA[6]
RDATA[9]
ATX
RDATA[8]
RDATA[11]
RDATA[14]
RDATA[7]
NAND_ALE
NAND_CLE
RDATA[0]
RDATA[1]
RDATA[3]
RDATA[4]
RDATA[5]
RDATA[7]
RDATA[6]
RDATA[2]
RDATA[3]
NAND_RBB
DQ[14]
DCLK
DADD[2]
DQ[10]
DQM0
DBA1
DQ[9]
DADD[9]
DQ[12]
DADD[1]
DADD[12]
DADD[6]
DQ[6]
DCASB
DQ[7]
DQ[8]
DADD[5]
DADD[0]
DVREF
DQ[4]
DQ[5]
DQ[11]
DQ[0]
DQ[3]
DADD[7]
DWEB
DVREF
DRASB
DADD[3]
DADD[10]
DQ[2]
DADD[11]
DQS1
DQ[1]
DCSB
DADD[4]
DQ[15]
DCLKB
DBA0
DQ[13]
DADD[8]
DQM1
DQS0
STRAP PINS
NAND FLASH
BIG ENDIAN
FULL MERGE
FULL MERGE
FIXED (DEBUG)
166MHz MAIN CPU CLOCK
166MHz MAIN CPU CLOCK
EDINT DISABLED
132.75 MHz DDR CLK
132.75 MHz DDR CLK
132.75 MHz DDR CLK
ROM BUS BIG ENDIAN
EXTERNAL BOOT
8 BIT MODE
NAND BOOT FCSB1
RESERVED
RESERVED
RESERVED
RDATA[0] = 1 -> MIPS32 IS BIG-ENDIAN
RDATA[2:1] = 10 -> FULL MERGE MODE
RDATA[3] = 0 -> FIXED (DEBUG)
RDATA[5:4] = 01 -> VRCLK = 166 MHz
RDATA[6] = 0 -> EDINT DISABLED
RDATA[9:7] = 011 -> MEMORY MCLK = 133 MHz
RDATA[10] = 1 -> ROM IS BIG ENDIAN
RDATA[11] = 0 -> NAND FLASH IS 256Mb OR LESS
RDATA[12] = 1 -> USE INTERNAL BOOT ROM
RDATA[15:13] = 000 -> USE NAND FLASH
ATX (SPDIF) = 1 -> USE FCS1B FOR NAND BOOT
PLACE THESE CAPACITORS CLOSE TO IC PINS.
DDR SDRAM
27MHZ CLOCK
PLACE THESE CLOSE TO PIN 49 OF IC
FIT FOR
EJTAG
JTAG
FIT FOR
PLACE ALL THE STRAP RESISTORS IN THE SAME LOCATION ON THE PWB
LAYOUT NOTE:-
REMOVE GND PLANE AROUND IC3201 AND X3200
AND ALSO FROM UNDERNEATH X3200 AND IC3201
INCLUDING TRACKS FROM XTAL TO IC.
N 2/7
N..-LE4B
TC58DVM72A1TG00
128-MB1T EEPROM
CRYSTAL CONTROLLED
OSCILLATOR
COMPONENTS MARKED AS XX ARE NOT FITTED ON THIS MODEL
DDR MEMORY