User guide

US 8,549,062 B2
9
power source is passed through the primary Winding of an
isolation transformer 604. A set of four AC-Line outputs 606
are then connected to the four IPT-IPM’s, e.g., 120-123 in
FIGS. 1 and 220-223 in FIGS. 2A and 2B. The voltage drop
across the primary Winding of isolation transformer 604 is
relatively small and insigni?cant, even at full load. So the line
voltage seen at the AC-Line outputs 606 is essentially the full
input line voltage.
A voltage is induced into a lightly loaded secondary Wind
ing that is proportional to the total current being draWn by all
the AC-loads, e.g., AC-receptacles 101-116 in FIGS. 1 and
201-216 in FIGS. 2A and 2B. An op-amp 608 is con?gured as
a precision recti?er With an output diode 610 and provides a
DC-voltage proportional to the total current being draWn by
all the AC-loads and passing through the primary of trans
former 604. An op-amp 612 ampli?es this DC-voltage for the
correct scale range for an analog-to-digital converter input
(A0) of a microcontroller (uC) 616. A Philips Semiconductor
type P87LPC767 microcontroller could be used for uC 616.
Such includes a built-in four-channel 8-bit multiplexed A/D
converter and an I2C communication port. When a READ
ADC command is received on the I2C communication port,
the A0 input is read in and digitally converted into an 8-bit
report value Which is sent, for example, to LED display 126 in
FIG. 1.
A prototype of the devices described in connection With
FIGS. 1-6 Was constructed. The prototype Was a combination
of neW hardWare and softWare providing for a 4-outlet, 8-out
let, or l6-outlet vertical-strip poWer manager that could be
accessed out-of-band on a single RJ45 serial port, or in-band
over a 10/ l00Base-T Ethernet connection by Telnet or an
HTML broWser. An R112 port Was connected to a second,
nearly identical vertical-strip poWer manager that Was almost
entirely a slave to the ?rst, e.g., it could only be controlled
by/via the ?rst/master vertical poWer manager.
Vertical poWer manager hardWare and softWare Was used
for the IPT-PS poWer supply board, the IPT-IPM quad-outlet
boards, and IPT-I2C peripheral/display board. For the master
vertical poWer manager, neW personality module hardWare
and softWare Was developed. This personality module, trade
marked SENTRY3, Was based upon the NetSilicon
NetARM+20M microprocessor, and provided all of the con
trol and user interface (U I). On the slave vertical poWer man
ager, a preexisting IPT-Slave personality module Was modi
?ed slightly to bridge the external and internal I2C-buses.
This alloWed the master to control the slave vertical poWer
manager exactly the same as the master vertical poWer man
ager, With no softWare or microprocessor needed on the slave.
NeW softWare couldbe included to run in a microprocessor on
the slave vertical poWer manager personality module to act as
a backup master for load-display and poWer-up sequencing
only.
A neW SENTRY3 personality module Was developed to
support an HTML interface for Ethernet, and a command-line
interface for Telnet and serial. Multiple users Were supported,
up to 128. One administrative user (ADMN) existed by
default, and Will default to having access to all ports. Outlet
grouping Was supported, With up to 64 groups of outlets.
There Were tWo I2C-buses that can support up to sixteen
quad-IPM (IPT-IPM) boards, across four poWer inputs, With
at mo st four quad-IPM’ s per input, and With each input having
its oWn load measurement and display. Each poWer input Was
required to have the same number of quad-IPM’s that it
poWered. There Was one I2C peripheral/display (IPT-I2C)
board for each poWer input. Each bus had only one smart
poWer supply (IPT-PS) board at 12C address 0x5E. Each bus
01
20
25
30
35
40
45
50
55
65
1 0
had at least one I2C peripheral/ display (IPT-I2C) board at I2C
address 0x50, and at least one quad-IPM (IPT-IPM) board at
I2C address 0x60 (or 0x40).
Determining What Was present on an I2C-bus, and at What
address, Was done by reading the 8-bit. I/O port of the poWer
supply. The eight bits Were con?gured as,
Bit 0 => Unde?ned
Bit 1 => Display orientation (1 = Upside-Up,
0 = Upside-Down)
Bit 2 => Number of quad-IPM’s per poWer input
Bit 3 => Number of quad-IPM’s per poWer input
Bit four => Overload point (1 = 30.5A [244ADC],
0 = 16.5A [132ADC])
Bit 5 => Unde?ned
Bit 6 => Number of poWer inputs
Bit 7 => Number of poWer inputs
Bits 2 & 3 together determine hoW many quad-IPM’s there
Were per poWer input. Bits 6 & 7 together determine hoW
many poWer input feeds there Were.
The I2C address of the quad-IPM’s Were determined by the
version of LPC code on the IPT-PS board, as determined by a
read of the STATus byte of the of the IPT-PS.
Version 3+ => quad-IPM’s start @ 0x60 and Were 0x60, 0x62,
0x64, 0x66, 0x68, 0x6A, 0x6C, 0x6E, 0x70,
0x72, 0x74, 0x76, 0x78, 0x7A, 0x7C, 0x7E.
quad-IPM’s start @ 0x40 and Were 0x40, 0x42,
0x44, 0x46, 0x48, 0x4A, 0x4C, 0x4E, 0x50,
Version 2- =>
Up to four IPT-I2C peripheral/display boards Were sup
ported at I2C addresses: 0x50, 0x52, 0x54, and 0x56.
There Was a direct mapping relationship betWeen poWer
inputs, IPT-I2C peripheral/ display boards I2C addresses, and
the IPT-IPM boards I2C addresses:
Power IPT-I2C IPT-IPM v3+ addresses
Input address (subtract 0x20 for v2—)
A 0x50 0x60, 0x62, 0x64, 0x66
B 0x52 0x68, 0x6A, 0x6C, 0x6E
C 0x54 0x70, 0x72, 0x74, 0x76
D 0x56 0x78, 0x7A, 0x7C, 0x7E
Considering that each input poWer feed can support up to
four quad-IPM’s (sixteen ports), and that each bus can have
four input feeds, and that there Were tWo I2C-buses, an
addressing scheme for a port must include three ?elds (a) Bus
ID, (b) Input Feed ID, and (c) Relay ID
The Bus ID could be regarded as vertical-strip poWer man
ager/enclosure ID, since one I2C-bus Were for the intemal/
local I2C vertical poWer manager components and the other
I2C-bus Were for the external/remote vertical poWer manager.
Other implementations could use a CAN bus in place of the
external I2C-bus. Each enclosure had an address on the bus,
e.g., an Enclosure ID. Thus, the three address ?elds needed
Were (a) Enclosure ID, (b) Input Feed ID, and (c) Relay ID.
The Enclosure ID Was represented by a letter, starting With
“A”, With a currently unde?ned maximum ultimately limited
to “Z”. Only “A” and “B” existed for the prototype. The Input
Feed ID Was represented by a letter, With a range of “A” to
“D”. The Relay ID Was represented by a decimal number,
With a range of“l” to “16”.