User guide

US 8,549,062 B2
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cycles. All four channels are converted once during each
1.042 ms, about 260 us apart. After four AC (60 HZ) cycles,
each channel has be converted 64 times. For each channel
these 64 conversions are averaged and stored. The most
recent eight stored averages are then again averaged, making
the reported value the truncated average over 64><8I512 AC
cycles, Which spans just over a half second.
The CRST command clears, the ReSeT Flag (RSTF)
PoWer On Reset Flag (PORF), BroWnOut Reset Flag
(BORE), and liiatchDog Reset Flag (WDRF) bits of the I/O
Expander status byte.
The WCFG command sets the microcontroller l/O con
?guration of the eight l/O pins. The WCFG command also
sets the read type to RCFG.
The WPRT command sets the state of the eight l/O pins that
are con?gured as outputs. The WPRT command also sets the
read type to RPRT.
The ADCE command enables or disables any or all four
ADC channels. The ADCE command also sets the read type
to RADC.
A read command is started by the master addressing the
slave With the R/W bit set. A read command to the slave
IPT-I2C microcontroller results in a ?xed number of bytes
repeatedly being transmitted by the slave (address, type,
data1 . . . dataN checksum). The ?rst byte is the address of the
slave. The second byte indicates the type of data in the data
bytes that folloW. The last byte is a checksum of all the
previous data bytes.
A Write command is started by the master addressing the
slave With the R/W bit cleared. This is folloWed by the master
transmitting multiple bytes to the slave, folloWed by a stop or
restart.
The lPT-PS module 218 digitally encodes the total AC
input current information onto the internal l2C-bus 219. The
lPT-PS module 218 derives DC-operating poWer from the
AC-poWer input for modules on the internal l2C-bus 219.
Each of the lPT-IPM modules 220-223 has four relays (K1
K4) that sWitch the AC-Line from the lPT-PS module 218 to
respective ones of the AC-Line connections on each of the
sixteen AC-output receptacles 201-216. Such relays K1-K4
are controlled by a single 12C transceiver located on each
lPT-IPM 220-223. For example, such 12C transceiver could
be implemented With a Philips microcontroller type
87LPC762.
Each such 12C transceiver is independently addressable on
the l2C-bus 219, and provides a digitally encoded poWer-on
status indication for all four relays K1-K4. An l2C-module
(IPT-I2C) 224 receives digital messages on the internal l2C
bus 219 and decodes and displays the totaliZed combined
current, e.g., in AC-amperes, on an LED-readout 226. The
internal l2C-bus 219 terminates at a lPT-NetWorkPM 228.
Preferably, lPT-NetWorkPM 228 includes an operating
system, an HTML Webpage, and a network interface. Such
can connect a remote user or command console With the
internal l2C-bus 219, an external l2C-bus that interconnects
With other outlet strips through a RJ-11 socket 230, an Eth
ernet 10/100 BaseT RJ-45 type socket 232, etc. The 1PT
NetWorkPM 228 preferably uses lntemet protocols like TCP/
IP and supports simple netWork management protocol
(SNMP).
The modular construction of outlet strip 200 alloWs a fam
ily of personality modules to be substituted for lPT-Net
WorkPM 228. Each such Would be able to communicate With
and control the lPT-lPM’s 220-223 via the internal l2C-bus
219.
The manufacturability and marketability of lPT-IPM 220
223 could be greatly enhanced by making the hardWare and
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softWare implementation of each the same as the others.
When a system that includes these is operating, it preferably
sorts out for itself hoW many lPM’s are connected in a group
and hoW to organize their mutual handling of control and
status data in and out.
FIG. 3 illustrates a printed circuit board (PCB) implemen
tation of an intelligent poWer module lPT-IPM 300, similar to
those of FIGS. 1, 2A, and 2B. On the component side of the
PCB, the lPT-IPM 300 has a tWo-position connector 302 for
AC-Neutral, and on the non-component side screW connector
304 for the AC-Line. A PCB trace 306 distributes AC-Line
poWer input to a series of four poWer control relays, as shoWn
in FIG. 4. An insulator sheet 310 screWs doWn over the IPT
IPM 300 and protects it from short circuits With loose Wires
and the sheetmetal outlet strip housing.
For example, insulator sheet 310 can be made of MYLAR
plastic ?lm and may not necessarily have a set of notches 312
and 314 that provide for connector tabs 302 and 304. Con
nector tabs 302 and 304 can alternatively be replaced With a
tWo-position connector With screW fasteners.
FIG. 4 illustrates the component side of a PCB implemen
tation of an lPT-IPM module 400, e. g., the opposite side vieW
of the lPT-IPM module 300 in FIG. 3. The lPT-IPM module
400 comprises a pair of 12C daisy chain bus connectors 402
and 404, a PCB trace 406 distributes AC-Line poWer input
from AC-Line screW connector 304 connect at a via 408 to a
series of four poWer control relays 410-413. A microcontrol
ler 414 processes the 12C communications on the internal
l2C-bus, e.g., l2C-bus 119 in FIGS. 1 and 219 in FIGS. 2A
and 2B.
FIG. 5 shoWs the basic construction of an lPT-NetWorkPM
module 500, and is similar to the lPT-NetWorkPM module
128 of FIGS. 1 and 228 of FIGS. 2A and 2B. A NetSilicon
(Waltham, Mass.) type NET+50 32-bit Ethernet system-on
chip for device netWorking is preferably used to implement a
communications processor 502. A ?ash memory 504 pro
vides program storage and a RAM memory 506 provides
buffer and scratchpad storage for the communications pro
cessor operations. A local l2C-bus is implemented in part
With a pair of 2N7002 transistors, for example. It connects
into the 12C daisy chain With a J1 -connector (CON4) 510. An
external l2C-bus is implemented inpart With a pair of 2N7002
transistors, for example. It connects into an external 12C
system With an RJ12-type J7-connector 510. Such external
12C system can expand to one additional outlet strip that
shares a single lPT-NetWorkPM module 500 and a single
netWork connection.
An Ethernet 10/100 BaseT interface With the media access
controller (MAC) internal to the communications processor
502 is provided by a physical layer (PHY) device 516. An
Intel type LXT971A fast Ethernet PHY transceiver, for
example, could be used together With an R145 connector 518.
A pair of RS-232 serial interfaces are implemented in part
With an SP3243E transceiver 520, an RJ45H connector 522,
another SP3243E transceiver 524, and an IDC10 connector
526.
The ?ash memory 504 is preferably programmed With an
operating system and HTML-browser function that alloW
Web-page type access and control over the Ethernet channel.
A complete OS kernel, NET+Management simple netWork
management protocol (SNMP) MlBll and proxy agent,
NET+Protocols including TCP/IP, NET+Web HTTP server,
and XML microparser, are commercially available from Net
Silicon for the NET+50 32-bit Ethernet system-on-chip.
FIG. 6 represents a circuit 600 that could be used in an
implementation of the lPT-PS 118 of FIG. 1 and lPT-PS 218
of FIGS. 2A and 2B. An AC-Line input 602 from the AC