User`s manual

Basic Operation & Standard Features
BASLER A620
f 3-1
DRAFT
3 Basic Operation and
Standard Features
3.1 Functional Description
3.1.1 Overview
A620f area scan cameras employ a CMOS-sensor chip which provides features such as a global
shutter and electronic exposure time control.
Normally, exposure time and charge readout are controlled by values transmitted to the camera’s
control registers via the IEEE 1394 interface. Control registers are available to set exposure time
and frame rate. There are also control registers available to set the camera for single frame
capture or continuous frame capture.
Exposure start can also be controlled via an externally generated trigger (ExTrig) signal. The
ExTrig signal facilitates periodic or non-periodic start of exposure. When exposure start is
controlled by a rising ExTrig signal and the camera is set for the programmable exposure mode,
exposure begins when the trigger signal goes high and continues for a pre-programmed period of
time. Accumulated charges are read out when the programmed exposure time ends.
The pixels can be connected to a bus and there is one bus per vertical column. At readout, the
pixels are addressed row-wise by closing a switch that connects each pixel in the addressed row
to the column buses. As the charges from the pixels leave the column buses, they are converted
to voltages and pass through the column amplifiers.
From the column amplifiers, the voltages enter an analog multiplexer that acts along with the X-
Addressing circuitry as a shift register. As the voltages are clocked out of the shift register, they
pass through an output amplifier and they are digitized by a 12 bit analog-to-digital converter
(ADC). The digitized video data next moves through a processing block in the FPGA that uses the
12 bit data to perform image correction functions and to perform the gain and offset functions. The
output from the processing block is pixel data at 10 bit depth. After processing, the data is directed
into an image buffer.
The data leaves the image buffer and passes back through the FPGA to a 1394 link layer
controller where it is assembled into data packets that comply with version 1.31 of the “1394 -
based Digital Camera Specification” (DCAM) issued by the 1394 Trade Association. The packets
are passed to a 1394 physical layer controller which transmits them isochronously to a 1394
interface board in the host PC. The physical and link layer controllers also handle transmission
and receipt of asynchronous data such as programming commands.