User`s manual

Basic Operation and Features
3-2 Basler A500k
PRELIMINARY
in the FPGA if 8 bit output is selected. The digital shifter selects the most significant 8 bits out of
the 10 bits for the A504
k, A503k, and A501k.
In the next step, different data flows occur:
•In the A504
k, the data is formatted to be output in 10 parallel data streams (10 taps).
•In the A503
k, the data is formatted to be output in 8 parallel data streams (8 taps)
•In the A501
k, the data is formatted to be output in 2 parallel data streams (2 taps).
The 8 Bit video data per pixel is transmitted from the camera to the frame grabber using a Camera
Link transmission format (see section 2.5 for details).
For optimal digitization, gain and offset are programmable via a serial port.
Figure 3-1: A500
k Sensor Architecture
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1
2
3
4
1024
Control
Logic
Ref
10 x 10 Bit
Digital 128 Stage Shift Register
10 x 10 x 128
CMOS-Sensor
Digital-Output Sensor
10
10
10
128 Cells
10
clear
Pixel
Memory