User`s manual

Camera Interface
2-30 Basler A500k
PRELIMINARY
• This pattern will continue until all of the pixel data for each data stream for line one has been
transmitted. (A total of 640 cycles for the A501
k.)
• Line valid becomes low for twenty pixel clocks.
• On the pixel clock cycle where data transmission for line two begins, the line valid bit will
become high. Two data streams are transmitted in parallel during this clock cycle. In each
data stream, 8 bits will contain the data for the first and second pixel of line number two.
• On the next cycle of the pixel clock, the line valid bit will be high. Two data streams are trans-
mitted in parallel during this clock cycle. In each data stream, 8 bits will contain the data for
the third and fourth pixel of line number two.
• On the next cycle of the pixel clock, the line valid bit will be high. Two data streams are trans-
mitted in parallel during this clock cycle. In each data stream, 8 bits will contain the data for
the fifth and sixth pixel of line number two.
• This pattern will continue until all of the pixel data for each data stream for line two has been
transmitted. (A total of 640 cycles.)
• After all of the pixels in line two have been transmitted, the line valid bit will become low for
twenty cycles indicating that valid data for line two is no longer being transmitted.
• The camera will continue to transmit pixel data for each line as described above until all of
the lines in the frame have been transmitted. After all of the lines have been transmitted, the
frame valid bit will become low at the same time as line valid indicating that a valid frame is
no longer being transmitted.
• Frame valid will remain low for at least 15 pixel clock cycles until the next frame starts.
Figure 2-12 shows the data sequence when the camera is operating in edge-controlled or level-
controlled exposure mode and Figure 2-13 shows the data sequence when the camera is
operating in programmable exposure mode.
Figure 2-12: 8 Bit Output Mode with Edge or Level-controlled Exposure for the A501k
ExSync
Signal
Frame
Valid
Line
Valid
Line 1 Line 2 Line 1024
Pixel
Clock
(50 MHz)
min. 3 µs
0.1 µs
0.4 µs 12.8 µs
13.2 µs
0 µs
13.517 ms
D_0
Pixel Data
(8 bits)
1277 127913
1279
1
1277 12791
D_1
Pixel Data
(8 bits)
1278 128024
1280
2
1278 12802
3
4
..5
..5
1
12
2
20
20 1
12
2
20
20
This diagram assumes that the area of interest feature is not being used. With the area of interest feature enabled, the
number of pixels transferred could be smaller.