User`s manual

Video Data Output Modes
Basler sprint Mono Cameras 105
5.2.3 8 Tap 8 Bit Output Mode
In 8 tap 8 bit output mode, on each pixel clock cycle, the camera transmits data for eight pixels at
8 bit depth, a line valid bit and a data valid bit.
In the 8 tap output mode, the camera uses the output ports on Camera Link Transmitters X, Y and
Z to transmit pixel data, a line valid bit, a data valid bit, and the Camera Link pixel clock. The
assignment of the bits to the output ports on Camera Link Transmitters X, Y and Z is as shown in
Table 21 on page 107, Table 22 on page 108, and Table 23 on page 109 respectively.
The Camera Link clock is used to time the transmission of acquired pixel data. As shown in
Figure 39 on page 110 and Figure 40 on page 111, the camera samples and transmits data on each
rising edge of the Camera Link clock. The Camera Link pixel clock frequency is as stated in
Section 2.8.4 on page 35.
The line valid bit indicates that a valid line is being transmitted. The data valid bit indicates that valid
pixel data is being transmitted. Pixel data is only valid when the line valid and data valid bits are
both high.
5.2.3.1 Video Data Sequence for 8 Tap 8 Bit Mode
When the camera is not transmitting valid data, the line valid and data valid bits sent on each cycle
of the pixel clock will be low. After the camera has completed a line acquisition, it will begin to send
data:
 On the clock cycle where valid pixel data transmission begins, the line valid and data valid bits
both become high. Eight data streams, D0 through D7 are transmitted in parallel during this
clock cycle. On this clock cycle, data stream D0 will transmit data for pixel 1 in the line. Data
stream D1 will transmit data for pixel 2. Data stream D2 will transmit data for pixel 3. Data
stream D3 will transmit data for pixel 4. Data stream D4 will transmit data for pixel 5. Data
stream D5 will transmit data for pixel 6. Data stream D6 will transmit data for pixel 7. And data
stream D7 will transmit data for pixel 8. The pixel data will be at 8 bit depth.
 On the next cycle of the pixel clock, the line valid and data valid bits will both be high. On this
clock cycle, data stream D0 will transmit data for pixel 9 in the line. Data stream D1 will
transmit data for pixel 10. Data stream D2 will transmit data for pixel 11. Data stream D3 will
transmit data for pixel 12. Data stream D4 will transmit data for pixel 13. Data stream D5 will
transmit data for pixel 14. Data stream D6 will transmit data for pixel 15. And data stream D7
will transmit data for pixel 16. The pixel data will be at 8 bit depth.
 On the next cycle of the pixel clock, the line valid and data valid bits will both be high. On this
clock cycle, data stream D0 will transmit data for pixel 17 in the line. Data stream D1 will
Note
The video data output mode that you select may affect the camera’s maximum
allowed line rate. See Section 4.3 on page 74.
The data sequence outlined below, along with Figure 39 on page 110 and
Figure 40 on page 111, describes what is happening at the inputs to the
Camera Link transmitters in the camera.