User`s manual

4,291,198
9
relay contacts DR3 in the handset are opened in the
circuit of the transmitter 73 for disabling that circuit
during the transmission of dialing signals from genera
tor 47. Also, contacts DR2 are opened to remove a
short circuit from a resistor 83 in the circuit of the re
ceiver 72 so that the dialing tone energy portion cou
pled back through hybrid network 71 is at an appropri
ately low level so that it does not disturb the user.
After each dialing tone has been transmitted for the
necessary called party number, processor 43 disables
dial relay 81 and thereby restores its associated contacts
to their normal condition. After all dialing tones have
been transmitted, the subscriber follows usual call
progress tones until the completion, or other dispo
sition, of his desired connection by the switch office.
After completion of voice signal exchange with the
called party, the subscriber hangs up by restoring hand
set 17 to its receptacle in the station set 10, the switch
hook switch opens its contacts H55 and thereby corre
spondingly signals processor 43 so that the processor
program can respond accordingly. The called number
display remains on the screen 13 until new data is sup
plied for the display area occupied by that number or
the display is otherwise cleared by user command. For
example, actuation of a RESET switch 45 in FIG. 4 by
the user clears screen 13 and reinitiates the program of
microprocessor 43.
For the purpose of data communication, processor 43
has a data input/output port coupled by way of a fur
ther multiconductor bidirectional bus 86 to the bit-par
allel transmit and receive ports of a universal asynchro
nous receive transmit (UART) circuit 89 such as the
Harris Corporation UART chip 6402-9. UART 89 also
has bit-series input/output connections to the outside
world by way of coupling logic 90 which is shown in
greater detail in FIG. 5. That logic further couples
UART signals by way of the circuit 22 to a host com
puter, either directly or via a data modem (not shown),
as will be further described in regard to FIG. 5. An
oscillator 87 has its output coupled to an input of a rate
selection circuit 88 which is controlled by a four-bit
output signal Sqb-3 from the option switches 57. The
signal from circuit 88 is sixteen times the bit rate and is
converted by logic in UART 89 to the required bit
series and bit-parallel clock signals for use in the
UART. Coupling logic 90 also receives from the
switches 57 an RS/CL signal indicating which of two
circuit interface standard signals is to be used and an
RM/LOC signal indicating whether remote or local
signals should control the screen 13 display. An addi
tional F D/HD signal from switches 57 informs proces
sor 43 whether the user has selected full duplex or half
duplex operation.
FIG. 5 is a gate level schematic diagram of the con
necting logic 90 in FIG. 4. Bit-series signals are coupled
from the UART 89 on an input circuit 91 and to the
UART on an output circuit 92. The output of coupling
logic 90 corresponding to the circuit 22 is one or the
other of the known RS232 (here RS) or current loop
(here CL) interface standards for signal source impe
dance, voltage and current levels. Separate circuits 22'
and 22" provide the selected standard coupling. Which
of the two output circuits 22' or 22" will be used at any
given time depends upon user selection of an RS/CL
option signal from the option switches 57 and comple
tion of a corresponding transmission circuit connection
to 22' or 22" at the back of the station set.
0
h. 5
25
35
40
50
55
60
65
10
Assuming ?rst that the RS serial data coupling mode,
e.g., to a modem, is selected by the RS/CL option sig
nal, the lead 91 signals are applied to one input of a
NAND gate 93 which also converts the signal from the
TTL levels to the RS standard levels. A low BRK
signal pulse from the keyboard, by way of processor 4&3
and a monostable trigger circuit 95, corresponds to
actuation ofa BREAK key 35. Otherwise when BRK is
high, gate 93 inverts data signals from lead 91 to serial
data output circuit 22’. The serial data input signal in
circuit 22’ is inverted by a single-input NAND gate 96,
which also converts the RS standard signals to the TTL
levels, before coupling to one input of NOR gate 97.
That gate has the RS/CL option signal applied to its
other input. Output of the gate 97 is coupled through a
further NOR gate 98 to the return lead 92 to the UART
89.
For current loop coupling to a host computer-based
service, the output of NAND gate 93 is inverted and
restored to the TTL levels in a single-input NAND gate
99. The output of that gate is coupled through an in
verter 100 to a signal limiting coupling element 101
including a current limiting resistor 102 and a shunt
limiting diode 103 connected to the positive supply.
Output from the element 101 is coupled through an
optical coupling element 104 including a light-emitting
diode 106 which cooperates with a photo transistor 107
to supply corresponding current loop signals to the
transmit loop of circuit 22". Similarly, the receive loop
of circuit 22" is applied in parallel across the light-emit
ting diode of receiving optical coupling element 109 and
the limiting diode of a signal limiting element 108. Ele
ments 108 and 109 have their respective resistor and
transistor connected in series between a positive supply
and ground. The midpoint between the resistor and
transistor of those two elements is coupled through
NAND gates 110, 111, and 112, and an inverter 113, to
a second input of the NOR gate 98.
NAND gate 112 has applied to another input thereof
the RS/CL option signal. When that option signal is
low, NAND gate 112 is blocked; and its corresponding
high output is coupled through inverter 113 as a low
input to enable the gate 98. Thus, the series input data is
inverted once in each of the gates 96 and the enabled 97
and 98 before reaching the lead 92. On the other hand,
when the RS/CL signal is high, gate 97 is blocked; and
gate 112 is enabled to couple data from NAND gate 111
through to the NOR gate 98.
The RM/LOC option signal is applied directly to one
input of NAND gate 110 and coupled through an in
verter 116 to a ?rst input of NAND gate 117. The same
input to gate 117 is also used as a LOCAL signal which
is applied to the processor 43 to keep it informed of the
circuit option selected by the user. Thus, one of gates
110 or 117 is always enabled and the other disabled.
When it is desired to receive input from a remote
source, the high RM/LOC signal enables gate 110 and
forces gate 117 to be disabled thereby enabling NAND
gate 111. The RS/CL signal must be high at this time
also so gate 112 is enabled to couple received data sig
nals from gate 111 on through NOR gate 98 toward the
UART 89. A low RM/LOC signal is inverted to enable
gate 117, and it blocks gate 110 thereby enabling gate
111. Input from the coupling element 109 is blocked, but
local output signal from the output of NAND gate 99 is
now coupled through an inverter 118 and the gates 117,
111, and 112 toward the UART. Thus, the user controls
the times either when the data output of the station set