Specifications

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into a discrete digital value, a serial UART (Universal Asynchronous
Receiver/Transmitter) for both intra-device communications as well as potential
inter-device communications with an output display, and any combination of
push-buttons and LEDs used for device initialization and status messages.
Based on these requirements, there are several candidate devices that will be
evaluated for their use in both devices. While it would be possible to utilize a
combination of different devices, based on the individual requirements of each
hardware unit, it would be advantageous for the selection of a single device to be
made in order to simplify both the hardware and software design aspects of this
project.
2.2.1 Application-Specific Integrated Circuit
Known more commonly by its acronym, an ASIC is an integrated circuit designed
for a very specific purpose, as opposed to a general purpose processor designed
for a variety of computational tasks. ASICs have the advantages of being
drastically lower in power consumption than comparable logic devices, as well as
having a significantly lower per-unit cost when factoring out the costs of ramping
up production of the chips. For any mass produced, complex digital device,
ASICs offer reduction to both production costs and system design complexity, as
there are fewer components to be concerned about supplying power and
communications for, and as such, fewer points of potential failure in the design.
Using manufacturer-specific tools, the process of designing an ASIC is usually an
iteration over the following steps.
1. Design Engineers begin with a non-formal understanding of the functions
required for the ASIC, usually going through a period of Requirements
Analysis to determine the level of functionality necessary
2. An initial design of the ASIC is created, using a Hardware Design
Language (HDL) to implement the necessary functional requirements for
the ASIC. This software is known as the Register-Transfer Level design.
3. The RTL design undergoes Functional Verification, where simulations of
device logic and functionality are conducted.
4. Logic Synthesis converts the RTL design into standard cells, or standard
collections of gate logic (2-input OR, AND, etc.), which are then
interconnected electrically. The result is known as the gate-level netlist.
5. The gate-level netlist is processed by software that routes and places the
logical cells into a specified area of the final proposed ASIC. It does this
using a set of Engineer-defined constraints, such as timing, power, and
heat, to determine the most optimum location for each cell.
6. A routing tool takes the gate-level netlist and the standard cells and
creates the mapping for electrical interconnection. The result is a physical
layout that can be passed on to a fabrication facility for production
7. Given a final design, a final simulation is conducted to determine that the
design will operate within the required parameters of timing, environment,