User's Manual

Product Brief – Airborne SDIO/SPI 802.11b/g Radio Quatech, Inc.
846-8310-240 June 2010 19
9.0 SDIO Interface
The Serial Data Input Output (SDIO) interface for the WLRG-RA-DP601 is detailed in the
following section. The interface is powered by the VHIO (pin 4 & 6) supply as defined in
Table 2. The interface is compliant to v1.0 of the SDIO interface standard.
9.1 SDIO Protocol Timing
The following figures and table define the required timing for the SDIO interface.
Figure 4 – SDIO Protocol Timing Diagram
SDIO Clock
Data OUT
Data IN
t
ODLY
f
PP
t
WL
Data OUT
Data IN
t
WH
t
ISU
t
IH
Figure 5 – SDIO Protocol Timing Diagram – High Speed
SDIO Clock
Data OUT
Data IN
t
OH
f
PP
t
WL
Data OUT
Data IN
t
WH
t
ODLY
t
ISU
t
IH