Specifications

80 Chapter 4—Simulation
Pin Delays and Inversion
The normal pin delay and inversion settings can be applied to the port inter-
face. A non–null value in the Invert.Pin attribute field will cause any signal
values passing in either direction to be inverted. An integer value in the
Delay.Pin attribute will cause the specified delay to be inserted inline with
level changes passing in either direction.
NOTE: 1) We recommend that pin delay and inversion settings be applied only to
the pin on the parent device, and not to the port connector in the internal
circuit. Attribute settings on the port connector are more difficult to verify
and edit, since the port connector is a “pseudo–device” and some
schematic editing operations will be disabled.
2) Changes made in the Invert.Pin and Delay.Pin attributes, after a device
has been placed on the schematic, will affect only that one device instance.
Default values can be set in these attribute fields when the symbol is
created in the DevEditor.
Power and Ground Connectors
Power and Ground connector symbols do not have any inherent simulation
signal drive, unless their pin type has been set to Tied High or Tied Low, as
appropriate. The positive–supply symbols provided with LogicWorks have
Tied High settings, while others will be Tied Low. The symbols provided
with older LogicWorks releases may not have any drive setting, resulting in a
high impedance level on these signals. This can be remedied by either:
 Replacing any one or all of the ground or power symbols with symbols
containing the appropriate setting; or
 Forcing a Stuck High or Stuck Low level onto the signal, using the
signal probe tool or the Stick Signals command. Note that, because all
like–named ground or power segments are logically connected, this
only needs to be done on a single segment.
LW Reference.bk Page 80 Monday, December 15, 2003 5:59 PM