Specifications

Signal Simulation Characteristics 61
Signal Simulation Characteristics
Signal States
LogicWorks uses 13 different device output states in order to track condi-
tions within your circuit. These states can be broken into three groups, as
follows:
Forcing States (denoted by suffix .F):
LOW.F
HIGH.F
DONT01.F
DONT0Z.F
DONT1Z.F
CONF.F
Resistive States (denoted by suffix .R):
LOW.R
HIGH.R
DONT01.R
DONT0Z.R
DONT1Z.R
CONF.R
High Impedance:
HIGHZ
Note that the Forcing/Resistive distinction is used only to resolve conflicts
between multiple outputs connected to the same signal. The final value
stored or displayed for a given signal line can only be one of five possibili-
ties:
LOW
HIGH
DONT
CONF
HIGHZ
LW Reference.bk Page 61 Monday, December 15, 2003 5:59 PM