Specifications

Simulation Primitive Types 237
D Flip-Flop with
Enable
Must have at least
D and CLK inputs
and Q output
S—set in
D—D in
C—clock in
E—enable in
R—reset in
Q—out
NQ—inverted out
1) S D C R Q NQ
2) S D C R Q
3) D C R Q NQ
4) D C R Q
5) D C Q NQ
6) D C Q
JK Flip-Flop Must have at least
CLK input and Q
output
S—set in
J—J in
K—K in
C—clock in
R—reset in
Q—out
NQ—inverted out
1) S J C K R Q NQ
¤
2) S T* C R Q NQ
¤
3) T* C R Q NQ
¤
4) C R Q NQ
¤
5) C Q NQ
¤
¤
NQ can always be
omitted
* T = J & K tied
together
Register N output bits
N input bits
1
IN
0
..IN
N-1
—in
CLK—in
CLR—in
OUT
0
..OUT
N-1
—out
1) IN
0
..IN
N-1
OUT
0
..OUT
N-1
CLK
CLR
2) IN
0
..IN
N-1
OUT
0
..OUT
N-1
CLK
Counter N output bits
N input bits
(optional)
1
IN
0
..IN
N-1
—in
CLK—in
LD—in
CLR—in
UP—in
EN—in
OUT
0
..OUT
N-1
—out
COUT—out
1) IN
0
..IN
N-1
OUT
0
..OUT
N-1
CLK
LD CLR UP EN COUT
2) IN
0
..IN
N-1
OUT
0
..OUT
N-1
CLK
LD CLR UP COUT
3) IN
0
..IN
N-1
OUT
0
..OUT
N-1
CLK
LD CLR COUT
4) IN
0
..IN
N-1
OUT
0
..OUT
N-1
CLK
LD COUT
5) IN
0
..IN
N-1
OUT
0
..OUT
N-1
CLK
COUT
Note: IN
0
..IN
N-1
&
LW Reference.bk Page 237 Monday, December 15, 2003 5:59 PM