Specifications

236 Appendix A— Primitive Device Pin Summary
Multiplexer L select inputs
M output bits 1
N inputs/ output
2
L-1
< N
L
( i.e., the number
of inputs per
output bit can be
less than the
number of select
input
combinations.)
S
0
..S
L-1
—in
IN
0,0
..IN
N-1,M-1
—in *
EN—in
¤
OUT
0
..OUT
M-1
—
out
* IN
n,m
is the input
routed to output m
when select value is
n.
¤
An enable input
can exist only if
N == 2
L
, otherwise
the extra input is
assumed to be a
data input.
1) IN
0,0
..IN
0,M-1
IN
1,0
..IN
1,M-1
..
IN
N-1,0
..IN
N-1,M-1
S
0
..S
L-1
OUT
0
..OUT
M-1
2) IN
0,0
..IN
0,M-1
IN
1,0
..IN
1,M-1
..
IN
0,0
..IN
N-1,M-1
S
0
..S
L-1
EN
OUT
0
..OUT
M-1
¤
¤
Option 2 only if
N == 2
L
Decoder L select inputs
M output bits 1
AND
2
L-1
< M
L
(i.e., the number of
output bits can be
less than the
number of select
input
combinations.)
S
0
..S
L-1
—in
EN—in
OUT
0
..OUT
M-1
—
out
1) OUT
0
..OUT
M-1
S
0
..S
L-1
2) OUT
0
..OUT
M-1
S
0
..S
L-1
EN
Adder,
Subtractor
N output bits
N “A” operand
inputs required
N “B” operand
inputs optional
1
A
0
..A
N-1
—in
B
0
..B
N-1
—in
CIN—in
SUM
0
..SUM
N-1
—
out
COUT—out
1) A
0
..A
N-1
B
0
..B
N-1
SUM
0
..SUM
N-1
CIN
COUT *
* B
0
..B
N-1
CIN &
COUT can be omitted in
any combination
D Flip-Flop, D
Latch
Must have at least
D, EN, and CLK
inputs and Q
output
S—set in
D—D in
C—clock in
R—reset in
Q—out
NQ—inverted out
1) S D C E R Q NQ
2) S D C E R Q
3) D C E R Q NQ
4) D C E R Q
5) D C E Q NQ
6) D C E Q
LW Reference.bk Page 236 Monday, December 15, 2003 5:59 PM