Specifications

LogicWorks 5 Description 3
Simulation Features
 Full digital simulation capability. Circuit output may be displayed in
the form of timing diagrams or on simulated output devices. Uses
thirteen signal states, including forcing and resistive drive levels to
correctly simulate circuits with design errors such as unconnected
inputs or conflicting outputs.
 Device delay time for individual primitive components may be set to
any integer from 0 to 32,767.
 The timing display has adjustable time-per-division and reference-line
placement.
 Common SSI and some MSI devices are implemented as primitives
with hard-coded simulation functions. These can be used to create
higher-level device functions. These primitive devices are “scalable,”
so you can create a 28-input AND gate or a 13-bit counter, for
example, as a single primitive device.
 Test and control devices, such as switches and displays, are active right
on the schematic diagram, allowing circuit operation to be directly
controlled and observed.
 A Clock generator device produces signals with variable period and
duty cycle. Any number of clock generators can exist in one circuit.
 Programmable Logic Arrays can be created with up to 256 inputs and
256 outputs with user-specified binary logic. When used with ABEL
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Student Edition Logic Compiler, PLA logic can be specified using
Boolean equations and state-transition logic. Programmable Read-
Only Memories with up to 16 inputs and 128 outputs can also be
simulated.
 A simulation control palette allows the circuit to be single-stepped or
run at various speeds.
 RAM devices of any configuration from 1 × 1 to 1Meg × 64 can be
created and simulated (based on available memory). Device options
include 0 or 1 OE inputs, 0 to 3 CE inputs, separate- or combined-data
I/O pins, and three-state or normal outputs.
LW Reference.bk Page 3 Monday, December 15, 2003 5:59 PM