Specifications

124 Chapter 7—RAMs and Programmable Devices
 Total PROM memory space < 2
31
bytes.
 Sufficient program memory free to allocate a block twice the size of
the simulated memory space.
PLA Device Characteristics
In LogicWorks, a PLA (Programmable Logic Array) models a group of
AND gates feeding into a single OR (active high) or NOR (active low) gate
for each output bit. Each AND-gate input is connected to either an input
bit, the inverse of an input bit, or constant high. By selectively making
these input connections, it is possible to determine which input combina-
tions will produce 0s or 1s in the outputs. PLAs are actually represented
internally in a compact binary format, not as a netlist of AND and OR
gates.
The input connections required to implement simple logic functions can
generally be determined “by eye” for simple cases, whereas more complex
logic must be reduced using Karnaugh maps, the Quine-McClusky method,
or other more advanced design techniques. These methods are discussed in
numerous circuit design textbooks and will not be covered here. Logic-
Works has the capability of reading device data produced by external logic
compiler programs.
PLA Size Limits
PLA devices must fall within the following limits:
 Number of Inputs: 1 to 128
 Number of Outputs: 1 to 128.
 Number of product terms per output <= 65,535.
Complex Programmable Logic Devices
The term Programmable Logic Device (as opposed to Programmable Logic
Array) will be used here to refer to a real programmable device that con-
sists of one or more AND-OR planes plus associated registers, buffers,
feedback paths, and so on. There is no PLD “primitive” device in Logic-
Works. Some very simple PLDs can be directly simulated with a single
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