Specifications

The RAM, PROM and PLA Primitive Types 123
RAM Pin Delay and Inversion Options
The normal options for pin delay (using the Delay.Pin attribute field) and
pin inversion (using the Invert.Pin attribute field) can be used with RAM
devices.
RAM Device Limitations
RAM devices must fall within all of the following limits:
 30 address-line inputs.
 256 bits per word.
 Total memory space < 2
31
bytes.
 Sufficient program memory free to allocate a block twice the size of
the simulated memory space.
NOTE: The Single Word Simulation option allows you to simulate a device with a
large number of address inputs without having to allocate memory for all
possible memory locations.
PROM Device Characteristics
For the purposes of simulation in LogicWorks, a PROM (Programmable
Read Only Memory) is defined as a device having N inputs (from 1 to 30)
and M outputs (from 1 to 256), and having 2
N
storage locations, each con-
taining M bits. Each different input combination selects one of the storage
locations, the contents of which appear on the output lines. The number of
storage locations required doubles for each input bit added, so PROM orga-
nization is only practical for a relatively small number of inputs. The
advantage of the PROM is that any arbitrary Boolean function can be rep-
resented simply by storing the truth table for the function in the appropriate
storage locations.
PROM Size Limits
PROM devices must fall within all of the following limits:
 30 address-line inputs.
 256 bits per word.
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