Specifications
122 Chapter 7—RAMs and Programmable Devices
RAM Device Characteristics
The RAM primitive device supports the direct simulation of static Random
Access Memory devices in a variety of configurations. You can create cus-
tom RAM devices with a variety of pin options.
This table summarizes the options available in the RAM primitive type.
Don’t Know Input Handling in RAM Devices
If any combination of Don’t Know values on the control inputs could cause
a write, then the selected memory location will be invalidated (that is, the
location will contain Don’t Know values). If the address inputs also have
Don’t Know values, then the entire device will be invalidated.
Chip Enables 0, 1, 2, or 3 active–low chip enables. If any chip–enable input
is high, all read and write functions are disabled. If no enable is
provided, the device will always be enabled.
Write Enable The active–low Write Enable pin is not optional. A low level
on the pin causes the data present at the Data In lines to be
written to the location selected by the address lines.
Output Enable Pin This active–low pin controls output enable but does not affect
writing.
Data In/Out The data input and output lines can either be separate or can be
combined into a single I/O bus.
Three–State
Outputs
If the input and output lines are combined, or if three–state
outputs are specified, the outputs enter a high impedance state
if Write Enable or any Chip Enable is high. If three–state
outputs are not specified, data outputs will be high when
disabled.
Single–Word
Simulation
If this option is selected, only a single word of real memory
will be allocated for simulation purposes (i.e., the address
inputs will be ignored). This allows logic testing of a circuit
containing a large RAM device without consuming large
amounts of program memory.
Common I/O This option specifies that a single I/O pin will be used per data
bit, rather than separate data in and data out lines. In this case,
three–state outputs are assumed and outputs will be disabled
when writing.
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