Specifications

Logic Devices 113
The following table illustrates some pin variations available for the Regis-
ter primitive type:
Counter
This device implements an N–bit, presettable, synchronous, positive-edge–
triggered, up/down counter with active–low enable. The load data inputs
and most of the control inputs can be omitted for simplified versions.
The following timing diagram shows a typical count cycle. Note that the
CO (Carry Out) output goes low when the count reaches 2
N
–1 (when
counting up) or 0 (when counting down), and rises again on the next count.
This can be used to cascade multiple counters together, as shown. The CLR
input clears the counter asynchronously (that is, regardless of the state of
the clock). The Count/Load input, when low, causes the data from the N
data inputs (D0–D3) to be passed to the outputs (Q0–Q3) on the rising edge
of the next clock. The Enable input disables counting when high, but has no
effect on loading.
4–bit register with active–high clear
4–bit register with active–low clear (using pin inversion)
4–bit register without clear
LW Reference.bk Page 113 Monday, December 15, 2003 5:59 PM