Specifications

112 Chapter 6—Primitive Devices

JK Flip–Flop

The JK flip–flop is negative-edge–triggered and obeys the following func-

tion table:

In the above table, X on the input side means Don’t Care and on the output

side means Don’t Know.

If any inputs are in an unknown state, the simulator will determine the out-

put state where possible, or else set it to Don’t Know.

 See the notes under D Flip–Flop, above, on setup and hold times and

initialization.

This device implements an N–bit, positive-edge–triggered register, with

common clock and optional active–high clear inputs.

 See the comments on Setup and Hold times and initialization in the

D Flip–Flop section, earlier in this chapter.

S R J K Clock Old Q New Q New Q/

0 0 XXX X 1 1

0 1 XXX X 1 0

1 0 XXX X 0 1

1100falls001

1100falls110

1 1 01fallsX0 1

1 1 10fallsX1 0

1111falls010

1111falls101

risesrisesXXX X X X

LW Reference.bk Page 112 Monday, December 15, 2003 5:59 PM