Datasheet

Seite 9
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SERIAL DIGITAL INTERFACE
3 Synchronous serial peripheral interface (SPI)
During an SPI transfer, data is simultaneously transmitted (shifted out serially) and
received (shifted in serially). A serial clock line synchronizes shifting and sampling of
the information on the two serial data lines. A slave select line allows individual selec-
tion of a slave SPI device; slave devices that are not selected do not interfere with SPI
bus activities. HYGROSENS ASIC’s SPI slave interface supports all combinations of
clock phase (CPHA) and polarity (CPOL). Slave CPOL and CPHA has to be
programmed to master adjustments before beginning of transmission. RAM/EEPROM
register 0x17
hex
contains initialization of SPI interface:
SFGSIF: SIFMD = interface mode SPI or I2C
SFGSIF: SPICKP = clock polarity CPOL
SFGSIF: SPICKE = clock phase CPHA
SPI Clock Phase and Polarity Controls
Software can select any of four combinations of serial clock (SCK) phase and polarity
using two bits in the SPI control register (SPCR). The clock polarity is specified by the
CPOL control bit, which selects an active high or active low clock and has no signifi-
cant effect on the transfer format. The clock phase (CPHA) control bit selects one of
two fundamentally different transfer formats.
CPHA Equals Zero Transfer Format
Fig. 12 shows a timing diagram of an SPI transfer where CPHA is zero. Two wave-
forms are shown for SCK: one for CPOL equals zero and another for CPOL equals
one. The diagram may be interpreted as a master or slave timing diagram since the
SCK, master in/slave out (MISO), and master out/slave in (MOSI) pins are directly
connected between the master and the slave. The MISO signal is the output from the
slave, and the MOSI signals the output from the master. The /SS line is the slave
select input to the slave.
Fig. 6: CPHA Equals Zero SPI Transfer Format – principle transfer illustration