Datasheet

Seite 5
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SERIAL DIGITAL INTERFACE
2 I
2
C Protocol
For I
2
C communication a data line (SDA) and a clock line (SCL) are required. The I
2
C
protocol used is defined as follows:
Idle period
During inactivity of the bus SDA and SCL are pulled-up to supply voltage VDDA.
Start condition
A high to low transition on SDA while SCL is at high level indicates a start condition.
Every command has to be initiated by a start condition sent by a master. A master can
always generate a start condition.
Stop condition
A low to high transition on SDA while SCL is at high level indicates a stop condition. A
command has to be closed by a stop condition to start processing the command
routine inside the IC.
SCL
SDA
start valid data proper stop
condition change condition
of data
Fig. 2: Principles of I
2
C protocol
Valid data
Data is transmitted in Bytes (8 Bits) starting with the most significant bit (MSB). Each
byte transmitted is followed by an acknowledge bit. Transmitted bits are valid if after a
start condition SDA keeps at constant level during high period of SCL. The SDA level
has to change only when clock signal at SCL is low.
Acknowledge
Acknowledge after transmitted byte is obligatory. The master must generate an
acknowledge related clock pulse. The receiver (slave or master) pulls-down the SDA
line during acknowledge clock pulse. If no acknowledge is generated by the receiver a
transmitting slave will set inactive. A transmitting master can abort the transmission by
generating a stop condition and may repeat the command.
A receiving master must signal the end of transfer to the transmitting slave by not
generating an acknowledge related clock pulse at SCL.
The HYGROSENS ASIC as a slave changes to inactive interface mode during
processing internal command routines started by a previously sent command.