Datasheet

Seite 12
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SERIAL DIGITAL INTERFACE
Transfer Ending Period
An SPI transfer is technically complete when the SPIF flag is set, but, depending on
the configuration of the SPI system, there may be additional tasks. Because the SPI
bit rate does not affect timing of the ending period, only the fastest rate will be consid-
ered in discussions of the ending period.
When the SPI is configured as a master, SPIF is set at the end of the eighth SCK
cycle. When CPHA equals one, SCK is inactive for the last half of the eighth SCK
cycle. Fig. 15 shows the transfer ending period for a master. The SCK waveforms in
this figure show only the CPOL equals zero case, since clock polarity does not affect
timing of the ending period.
Fig. 9: Transfer Ending for an SPI Master
When the SPI is operating as a slave, the ending period is different because the SCK
line can be asynchronous to the MCU clocks of the slave and because the slave does
not have access to as much information about SCK cycles as the master. For
example, when CPHA equals one, where the last SCK edge occurs in the middle of
the eighth SCK cycle, the slave has no way of knowing when the end of the last SCK
cycle is. For these reasons, the slave considers the transfer complete after the last bit
of serial data has been sampled, which corresponds to the middle of the eighth SCK
cycle. A synchronization delay is required so the setting of the SPIF flag is properly
positioned relative to the internal clock of the slave. Fig. 16 shows the ending period
for a slave. The SCK waveforms in this figure show only the CPOL equals zero case,
since clock polarity does not affect timing of the ending period.
Fig. 10: Transfer Ending for an SPI Slave