Datasheet

Seite 11
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SERIAL DIGITAL INTERFACE
Beginning and Ending SPI Transfers
A transfer includes the eight SCK cycles plus an initiation period at the beginning and
ending period of the transfer. The details of the beginning and ending periods depend
on the CPHA format selected and whether the SPI is configured as a master or a
slave. The initiation delay period is also affected by the SPI clock rate selection when
the SPI is configured as a master.
It may be useful to refer to the transfer format illustrated in Fig. 12 and Fig. 13 to
understand how the beginning and ending details fit into a complete transfer opera-
tion.
Transfer Beginning Period (Initiation Delay)
All SPI transfers are started and controlled by a master SPI device. As a slave the
transfer to begin with the first SCK edge or the falling edge of /SS, depending on the
CPHA format selected. When CPHA equals zero, the falling edge of /SS indicates the
beginning of a transfer. When CPHA equals one, the first edge on the SCK indicates
the start of the transfer. In either CPHA format, a transfer can be aborted by taking the
/SS line high, which causes the SPI slave logic and bit counters to be reset. The SCK
rate selected has no effect on slave operations since the clock from the master is
controlling transfers.
CPHA has no effect on the delay to the start of the transfer, but it does affect the initial
state of the SCK signal. When CPHA equals zero, the SCK signal remains inactive for
the first half of the first SCK cycle. When CPHA equals one, the first SCK cycle begins
with an edge on the SCK line from its inactive to its active level. The SPI clock rate
(selected by SPR[1:0]) affects the delay from the write to SPDR and the start of the
SPI transfer (see Fig. 14). The internal SPI clock in the master is a free-running deriv-
ative of the internal MCU clock. Since the SPI clock is free-running, there is an uncer-
tainty about the write operation to SPDR will occur relative to the slower SCK. This
uncertainty causes the variation in the initiation delay shown in fig. 8.
Fig. 8: Delay from Write SPDR to Transfer Start (Master)