Datasheet

Seite 10
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SERIAL DIGITAL INTERFACE
CPHA Equals One Transfer Format
Fig. 13 shows a timing diagram of an SPI transfer where CPHA is one. Two wave-
forms are shown for SCK: one for CPOL equals zero and another for CPOL equals
one. The diagram may be interpreted as a master or slave timing diagram since the
SCK, MISO, and MOSI pins are directly connected between the master and the slave.
The MISO signal is the output from the slave, and the MOSI signal is the output from
the master. The /SS line is the slave select input to the slave.
Fig. 7: CPHA Equals One SPI Transfer Format – principle transfer illustration
When CPHA equals zero, the /SS line must be negated and reasserted between each
successive serial byte. Also, if the slave writes data to the SPI data register (SPDR)
while /SS is active low, a write-collision error results.
When CPHA equals one, the /SS line may remain active low between successive
transfers (can be tied low at all times). This format is sometimes preferred in systems
having a single fixed master and a single slave driving the MISO data line.
SPI Pin Signals
There are four I/O pin signals associated with SPI transfers: the SCK, the MISO data
line, the MOSI data line, and the active low /SS pin. When the master initiates a
transfer, eight clock cycles are automatically generated on the SCK pin. The SCK pin
is an input and the clock signal from the master synchronizes the data transfer
between the master and slave devices. Slave devices ignore the SCK signal unless
the /SS pin is active low. In both the master and slave SPI devices, data is shifted on
one edge of the SCK signal and is sampled on the opposite edge where data is stable.
Edge polarity is determined by the SPI transfer protocol.
The MISO and MOSI data pins are used for transmitting and receiving serial data. At
slave MOSI is the data input line, and MISO is the data output line. One by master
selected slave device optionally drives data out its MISO pin to the MISO master pin.
The automatic control of the direction of these pins makes reconfiguration through
external logic unnecessary when a new device becomes the master.
The /SS pin behaves differently on master and slave devices. On a slave device, this
pin is used to enable the SPI slave for a transfer. If the /SS pin of a slave is inactive
(high), the device ignores SCK clocks and keeps the MISO output pin in the high-
impedance state.