Serial Digital Interface of HYGROSENS ASIC Protocol of I2C Interface SPI Interface
Index............................................................................................................................................2 Manufacturer Informations...........................................................................................................2 1 General Description...................................................................................................................3 2 I2C Protocol...............................................................................
HYGROSENS INSTRUMENTS GmbH Postf ach 1054 The HYGROSENS ASIC includes a serial digital interface, which is able to communicate using two different communication protocols – I2C and SPI –communication. The serial digital interface allows the programming of the EEPROM to configure the application mode of the ASIC and to calibrate the conditioning equation. Furthermore it makes possible the read out of the conditioning result of measurand and both temperatures as digital 15 Bit values.
not in manufacturing mode Initialization and configuration NON I2 C SPI manufactoring interface OWI Initialization Window (20ms) Send Start_CM Diagnostic mode Command MODE WRITE Commands Calibration READ Command NORMAL MODE (W ith analog output) COMMAND MODE General working mode Fig.
For I2C communication a data line (SDA) and a clock line (SCL) are required. The I 2C protocol used is defined as follows: Idle period During inactivity of the bus SDA and SCL are pulled-up to supply voltage VDDA. Start condition A high to low transition on SDA while SCL is at high level indicates a start condition. Every command has to be initiated by a start condition sent by a master. A master can always generate a start condition.
The general HYGROSENS ASIC slave address is 0x78 (7bit). As the address is completed with the R/W-Bit as LSB the address Byte (whole 8 bit) for reading data is 0xA1 for reading or 0xA0 for writing data to the ASIC. By EEPROM programming it is possible to allocate and activate an additional arbitrary slave address to every single device. In this case the device recognizes communication on both addresses, on the general one and on the activated one.
tI2C_SU_STA tI2C_HD_STA tI2C_SU_DAT tI2C_HD_DAT SDA tI2C_H tI2C_L SCL tI2C_SU_STO tI2C_HD_STA SDA tI2C_BF Fig. 5: Timing I2C protocol Nr. Parameter Symbol 1 SCL Clock frequency fSCL 2 Bus free time betw. start and stop tI2C_BF condition 1.3 µs 3 Hold time start condition tI2C_HD_STA 0.6 µs 4 Setup time condition start tI2C_SU_STA 0.6 µs 5 Low period SCL/SDA tI2C_L 1.3 µs 6 High period SCL/SDA tI2C_H 0.
t_050 "set switch-off time to 50 ms" t01200 "select trigger channel KS5V with a trigger time of 200 ms" iwt7800172 "write command 0x72 to address 0x78 with trigger" iw_7800152 "configure SIF to communication mode I2C" iw_7800171 "start Normal Operation Mode" t00000 "turn OFF the trigger channel ==> KS5V = OFF" The command 0x52 is configurating the serial interface for I2C communication.
During an SPI transfer, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). A serial clock line synchronizes shifting and sampling of the information on the two serial data lines. A slave select line allows individual selection of a slave SPI device; slave devices that are not selected do not interfere with SPI bus activities. HYGROSENS ASIC’s SPI slave interface supports all combinations of clock phase (CPHA) and polarity (CPOL).
When CPHA equals zero, the /SS line must be negated and reasserted between each successive serial byte. Also, if the slave writes data to the SPI data register (SPDR) while /SS is active low, a write-collision error results. When CPHA equals one, the /SS line may remain active low between successive transfers (can be tied low at all times). This format is sometimes preferred in systems having a single fixed master and a single slave driving the MISO data line.
A transfer includes the eight SCK cycles plus an initiation period at the beginning and ending period of the transfer. The details of the beginning and ending periods depend on the CPHA format selected and whether the SPI is configured as a master or a slave. The initiation delay period is also affected by the SPI clock rate selection when the SPI is configured as a master. It may be useful to refer to the transfer format illustrated in Fig. 12 and Fig.
Fig. 9: Transfer Ending for an SPI Master When the SPI is operating as a slave, the ending period is different because the SCK line can be asynchronous to the MCU clocks of the slave and because the slave does not have access to as much information about SCK cycles as the master. For example, when CPHA equals one, where the last SCK edge occurs in the middle of the eighth SCK cycle, the slave has no way of knowing when the end of the last SCK cycle is.
HYGROSENS INSTRUMENTS GmbH Postf ach 1054 Technische Änderungen v orbehalten! Ausgabe 08/2008 When CPHA equals zero, there is a potential problem that can be avoided by proper software but is sometimes overlooked. The SPIF flag is set at the end of a transfer, but the slave is not permitted to write new data to the SPDR while the /SS line is still low. If the master device is busy, the /SS line to the slave can remain low longer than the slave expects.
Command (HEX) Data Command Remarks Processing time System clock 2MHz 01 START_CYC_EEP Start measurement cycle including initialization from EEPROM 350µs 02 START_CYC_RAM Start measurement cycle including initialization from RAM 220µs 10 .. 1F READ_RAM0 Read data from RAM address 00 .. 0F Writes data from RAM to SIF Output Registers Usually followed by Read operation 50µs 20 .. 2F READ_RAM1 Read data from RAM address 10 ..
Command Remarks Processing time System clock 2MHz / EEPROMProgr. Steps 80 .. 8F 2 Byte WRITE_RAM0 Write data to RAM address 00 .. 0F 50µs 90 .. 9F 2 Byte WRITE_RAM1 Write data to RAM address 10 .. 1F 50µs A0 .. AF 2 Byte WRITE_EEP0 Write data to EEPROM address 00 .. 0F 12.5ms / 1 B0 .. BF 2 Byte WRITE_EEP1 Write data to EEPROM address 10 .. 1F 12.
Issued August 2008 - This documentation supersedes all previous editions. © Copyright 2008 HYGROSENS INSTRUMENTS GmbH. All rights reserved. No part of this documentation is allowed to be stored, reproduced, processed, duplicated or published in any form without prior written permission from the company HYGROSENS INSTRUMENTS GmbH. Ausgabe 08/2008 The technical information in this document has been checked with adequate care at our end and is intended to inform about the product and its applications.
