Specifications

Si3216
Rev. 1.0 47
Not Recommended
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the command/address byte indicate the address of the
register to be accessed. The second byte of the pair is
the data byte. During a read operation, the SDO
becomes active, and the 8-bit contents of the register
are driven out MSB first. The SDO will be high
impedence on either the falling edge of SCLK following
the LSB or the rising edge of CS
, whichever comes first.
SDI is a “don’t care” during the data portion of read
operations. During write operations, data is driven into
the ProSLIC via the SDI pin MSB first. The SDO pin
remains high-impedance during write operations. Data
always transitions with the falling edge of the clock and
is latched on the rising edge. The clock should return to
a logic high when no transfer is in progress.
There are a number of variations of usage on this four-
wire interface:
 Continuous clocking. During continuous clocking,
the data transfers are controlled by the assertion of
the CS
pin. CS must assert before the falling edge of
SCLK on which the first bit of data is expected during
a read cycle and must remain low for the duration of
the 8 bit transfer (command/address or data).
 SDI/SDO wired operation. Independent of the
clocking options described, SDI and SDO can be
treated as two separate lines or wired together if the
master is capable of tristating its output during the
data byte transfer of a read operation.
 Daisy chain mode. This mode allows
communication with banks of up to eight ProSLIC
devices using one chip select signal. When the
SPIDC bit in the SPI Mode Select register is set,
data transfer mode changes to a 3-byte operation: a
chip select byte, an address/control byte, and a data
byte. Using the circuit shown in Figure 28, a single
device may select from the bank of devices by
setting the appropriate chip select bit to “1”. Each
device uses the LSB of the chip select byte, shifts
the data right by one bit, and passes the chip select
byte using the SDITHRU pin to the next device in the
chain. Address/control and data bytes are unaltered.
Figure 26. Serial Write 8-Bit Mode
Figure 27. Serial Read 8-Bit Mode
SCLK
CS
SDI
SDO
High Impedance
0
a0a1a2a3a4a5a6 d7 d0d1d2d3d4d5d6
Don't Care
SCLK
CS
SDI
SDO
1
a0a1a2a3a4a5a6
d7 d0d1d2d3d4d5d6
Don't Care
High Impedance
Don't Care