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Si3216

PROSLIC

PROGRAMMABLE WIDEBAND SLIC/CODEC

WITH RINGING/BATTERY VOLTAGE GENERATION

Features

Applications

Description

The Si3216 ProSLIC

is a low-voltage CMOS device that provides a complete analog

telephone interface supporting both wideband (50 Hz to 7.0 kHz) and narrowband

(200 Hz to 3.4 kHz) audio codec modes for enhanced voice quality in Voice-over-IP

(VoIP) applications. The ProSLIC integrates subscriber line interface circuit (SLIC),

wideband voice codec, and battery generation functionality into a single fully-

programmable device for global operation using only one hardware solution. The

Si3216’s wideband codec provides expanded audio band (50 Hz to 7 kHz), 16 kHz

sampling rate, and increased dynamic range for improved audio quality over traditional

telephony codecs. The integrated battery supply continuously adapts its output voltage

to minimize power and enables the entire solution to be powered from a single 3.3 V

(Si3216M only) or 5 V supply. Si3216 features include software-configurable 5 REN

internal ringing up to 90 V

, DTMF and caller ID generation, and a comprehensive set

of telephony signaling capabilities including expanded support of Japan and China

country requirements. The ProSLIC is packaged in a 38-pin QFN and TSSOP, and the

Si3201 high-voltage line interface device is packaged in a thermally-enhanced 16-pin

SOIC.

Functional Block Diagram

 Dual-mode wideband (50 Hz to 7 kHz)/

narrowband (200 Hz to 3.4 kHz) codec with

16-bit 16 kHz sampling for enhanced audio

quality

 Performs all BORSCHT functions

 Ideal for customer premise equipment

applications

 Software-programmable internal ringing up

to 90 V

 Integrated battery supply with dynamic

voltage output

On-chip dc-dc converter continuously

minimizes power in all operating modes

Entire solution can be powered from a

single 3.3 V or 5 V supply

3.3 V to 35 V dc input range

Dynamic 0 V to –94.5 V output

Low-cost inductor and high-efficiency

transformer versions supported

 Software-programmable features and

parameters:

Ringing frequency, amplitude, cadence,

and waveshape

2-wire ac impedance and hybrid

Constant current feed (20 to 41 mA)

Loop closure and ring trip thresholds



Software programmable signal

generation and audio processing:

µ-law/A-law companding

FSK (caller ID) generation

Dual audio tone generators

Smooth and abrupt polarity reversal

 100% software-configurable global

solution

 Audio loopback, dc, and GR-909

subscriber line diagnostic capabilities

 Lead-free and RoHS-compliant packages

available

 Voice-over-broadband systems:

DSL, cable, wireless

 PBX/IP-PBX/key telephone systems

 Terminal adapters: ISDN, Ethernet, USB

Control

Interface

Tone

Generation

Expansion

Compression

PLL

PCM

Interface

Dual-Mode

Wideband/

Narrowband

Codec

Prog.

Hybrid

Linefeed

Control

Discrete

Components

DC-DC Converter Controller

Linefeed

Interface

Line

Status

INT RESET

SCLK

SDO

SDI

DTX

FSYNC

PCLK

DRX

TIP

RING

Si3216

U.S. Patent #6,567,521

U.S. Patent #6,812,744

Other patents pending

Ordering Information

See page 114.

Pin Assignments

Si3216

34 33 32

35363738

15 16 17 18 19

QFN

DTX

FSYNC

RESET

SDCH

SDCL

DDA1

IREF

CAPP

QGND

CAPM

STIPDC

SRINGDC

STIPE

SVBAT

SRINGE

STIPAC

RINGAC

IGMN

GNDA

IGMP

IRINGN

IRINGP

DDA2

ITIPP

ITIPN

VDDD

GNDD

TEST

DCFF

DCDRV

SDITHRU

SDO

SDI

SCLK

INT

PCLK

DRX

Summary of content (123 pages)

PAGE 1
Si3216 P RO SLIC ® P R O GRA MM A B LE W IDEBAND SLIC/C ODEC W I T H R INGING / B A TT E R Y V OLTA GE G ENERATION Features   Software-programmable features and parameters: Ringing frequency, amplitude, cadence, and waveshape 2-wire ac impedance and hybrid Constant current feed (20 to 41 mA) Loop closure and ring trip thresholds  Software programmable signal generation and audio processing: Ordering Information See page 114.
PAGE 2
N ot fo R r N ec e w om m D e e s nd ig e ns d Si3216 2 Rev. 1.
PAGE 3
Si3216 TABLE O F C ONTENTS Section Page N ot fo R r N ec e w om m D e e s nd ig e ns d 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.1. Linefeed Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.2.
PAGE 4
Si3216 1. Electrical Specifications Table 1. Absolute Maximum Ratings and Thermal Information1 Parameter Symbol Value Unit VDDD, VDDA1, VDDA2 –0.5 to 6.0 V IIN ±10 mA VIND –0.3 to (VDDD + 0.
PAGE 5
Si3216 Table 2. Recommended Operating Conditions Symbol Test Condition Min* Typ Max* Unit Ambient Temperature TA K-grade 0 25 70 oC Ambient Temperature TA B-grade –40 25 85 o Si3216 Supply Voltage VDDD,VDDA1, VDDA2 3.13 3.3/5.0 5.25 V Si3201 Supply Voltage VDD 3.13 3.3/5.0 5.
PAGE 6
Si3216 Table 3. AC Characteristics—Wideband Audio Mode: Si3216 (VDDA, VDDD = 3.13 to 5.25 V, TA = 0 to 70 °C for K-Grade, –40 to 85 °C for B-Grade) Parameter Test Condition Min Typ Max Unit TX/RX Performance—Wideband Audio Mode Overload Level Single Frequency Distortion 1 2.5 — — VPK 2-wire – PCM or PCM – 2-wire: 50 Hz–7.0 kHz — — –45 dB 50 Hz–7.
PAGE 7
Si3216 Table 3. AC Characteristics—Wideband Audio Mode: Si3216 (Continued) (VDDA, VDDD = 3.13 to 5.
PAGE 8
Si3216 (dB) +1 –4.5 100 6.4k 7k 8k 9k (Hz) N ot fo R r N ec e w om m D e e s nd ig e ns d 50 –1 –25 –45 Figure 1. Transmit and Receive Path Attenuation Distortion—Wideband Mode (ms) 4 2 1 0.25 50 100 300 4k 6.4k 7k (Hz) Figure 2. Transmit and Receive Path Group Delay Distortion—Wideband Mode 8 Rev. 1.
PAGE 9
Si3216 Table 4. AC Characteristics—Narrowband Audio Mode (VDDA, VDDD = 3.13 to 5.25 V, TA = 0 to 70 °C for K-Grade, –40 to 85 °C for B-Grade) Parameter Test Condition Min Typ Max Unit TX/RX Performance—Narrowband Audio Mode Overload Level THD = 1.5% 2.5 — — VPK 2-wire – PCM or PCM – 2-wire: 200 Hz–3.4 kHz — — –45 dB 200 Hz–3.
PAGE 10
Si3216 Table 4. AC Characteristics—Narrowband Audio Mode (Continued) (VDDA, VDDD = 3.13 to 5.25 V, TA = 0 to 70 °C for K-Grade, –40 to 85 °C for B-Grade) Parameter Test Condition Min Typ Max Unit Noise Performance—Narrowband Audio Mode C-Message Weighted — — 15 dBrnC Psophometric Weighted — — –75 dBmP 3 kHz flat — — 18 dBrn PSRR from VDDA RX and TX, DC to 3.4 kHz 40 — — dB PSRR from VDDD RX and TX, DC to 3.
PAGE 11
N ot fo R r N ec e w om m D e e s nd ig e ns d Si3216 Figure 3. Transmit and Receive Path SNDR—Narrowband Mode 9 8 7 6 Fundamental Output Power 5 (dBm0) Acceptable Region 4 3 2.6 2 1 0 1 2 3 4 5 6 7 8 9 Fundamental Input Power (dBm0) Figure 4. Overload Compression Performance Rev. 1.
PAGE 12
Si3216 N ot fo R r N ec e w om m D e e s nd ig e ns d Typical Response Typical Response Figure 5. Transmit Path Frequency Response—Narrowband Mode 12 Rev. 1.
PAGE 13
N ot fo R r N ec e w om m D e e s nd ig e ns d Si3216 Figure 6. Receive Path Frequency Response—Narrowband Mode Rev. 1.
PAGE 14
N ot fo R r N ec e w om m D e e s nd ig e ns d Si3216 Figure 7. Transmit Group Delay Distortion—Narrowband Mode Figure 8. Receive Group Delay Distortion—Narrowband Mode 14 Rev. 1.
PAGE 15
Si3216 Table 5. Linefeed Characteristics (VDDA, VDDD = 3.13 to 5.
PAGE 16
Si3216 Table 6. Monitor ADC Characteristics (VDDA, VDDD = 3.13 to 5.25 V, TA = 0 to 70 °C for K-Grade, –40 to 85 °C for B-Grade) Parameter Symbol Test Condition Min Typ Max Unit Differential Nonlinearity (6-bit resolution) DNLE –1/2 — 1/2 LSB Integral Nonlinearity (6-bit resolution) INLE –1 — 1 LSB — — 10 % 20 % N ot fo R r N ec e w om m D e e s nd ig e ns d Gain Error (voltage) Gain Error (current) — — Table 7. Si321x DC Characteristics, VDDA = VDDD = 5.0 V (VDDA, VDDD = 4.
PAGE 17
Si3216 Table 9. Power Supply Characteristics (VDDA,VDDD = 3.13 to 5.25 V, TA = 0 to 70 °C for K-Grade, –40 to 85 °C for B-Grade) Parameter Power Supply Current, Analog and Digital Symbol Test Condition Typ1 Typ2 Max Unit IA + ID Sleep (RESET = 0) 0.1 0.13 0.3 mA Open 33 42.
PAGE 18
Si3216 Table 10. Switching Characteristics—General Inputs VDDA = VDDA = 3.13 to 5.25 V, TA = 0 to 70 °C for K-Grade, –40 to 85 °C for B-Grade, CL = 20 pF) Parameter Symbol Min Typ Max Unit Rise Time, RESET tr — — 20 ns RESET Pulse Width trl 100 — — ns Note: All timing (except Rise and Fall time) is referenced to the 50% level of the waveform. Input test levels are VIH = VD – 0.4 V, VIL = 0.4 V. Rise and Fall times are referenced to the 20% and 80% levels of the waveform.
PAGE 19
Si3216 tthru tr tr tc SCLK tsu1 th1 CS tcs th2 N ot fo R r N ec e w om m D e e s nd ig e ns d tsu2 SDI td1 td2 td3 SDO Figure 9. SPI Timing Diagram Table 12. Switching Characteristics—PCM Highway Serial Interface VD = 3.13 to 5.25 V, TA = 0 to 70 °C for K-Grade, –40 to 85 °C for B-Grade, CL = 20 pF Parameter Symbol Test Conditions Min 1 Typ 1 Max 1 Units MHz MHz MHz MHz MHz MHz MHz MHz % PCLK Frequency 1/tc — — — — — — — — 0.256 0.512 0.768 1.024 1.536 2.048 4.096 8.
PAGE 20
Si3216 tr tc tf PCLK th1 tsu1 FSYNC tsu2 th2 N ot fo R r N ec e w om m D e e s nd ig e ns d DRX td2 td1 td3 DTX Figure 10. PCM Highway Interface Timing Diagram VCC C3 220 nF STIPAC 27 30 VDDD 10 23 GNDD VDDA2 STIPDC 20 VDDA1 15 GNDA TEST R1 200k C24 0.1  F 31 32 VCC 38 SCLK SDI R8 4.7K IRINGN 13 25 IRINGN ITIPP 16 28 ITIPP 14 26 IRINGP 17 STIPE 19 SRINGE R4 196k SRINGE 10 R291 2 Note 2 7 R26 2 40.
PAGE 21
Si3216 Table 13. Si3216(M) + Si3201 External Component Values Value Supplier C1,C2 10 µF, 6 V Ceramic or 16 V Low Leakage Electrolytic, ±20% Murata, Nichicon URL1C100MD C3,C4 220 nF, 100 V, X7R, ±20% Murata, Johanson, Novacap, Venkel C5,C6 22 nF, 100 V, X7R, ±20% Murata, Johanson, Novacap, Venkel C15,C16,C17,C24 0.1 µF, 6 V, Y5V, ±20% Murata, Johanson, Novacap, Venkel C18,C19 4.
PAGE 22
Si3216 32 31 23 10 27 30 TEST GNDA VDDA1 VDDA2 VDDD GND GNDD VCC R1 200k 15 GND 20 29 Q6 5551 C5 22nF C324 0.1 µF C8 220nF R13 5.1k PCLK ITIPN DRX STIPE R2 100k R6 80.6 DTX 37 SPI Bus 36 1 6 3 4 PCM Bus 5 VCC R322 10k 18 R104 (100k) R7 80.6 C4 220nF R9 4.7k 21 16 C26 0.1uF R21 15 SVBAT SRINGAC SRINGDC R3 200k GND IGMP 9 Q9 2N2222 SDCL VCC R291 R281 7 Note 2 R262 40.2k 24 IGMN 22 IREF 11 CAPP 12 CAPM 14 QGND 13 DCFF R5 100k C33 4 0.
PAGE 23
Si3216 Table 14. Si3216(M) External Component Values (Continued) 200 k, 1/10 W, 1% R2,R4,R5, R102,R104,R105 100 k, 1/10 W, 1% R6,R7 80.6 , 1/4 W, 1% R8,R9 4.7 k, 1/10 W, 1% R10,R11 10 , 1/10 W, 5% R12,R13 5.1 k, 1/10 W, 5% R14,R26* 40.
PAGE 24
Si3216 Table 15. Si321x BJT/Inductor DC-DC Converter Component Values Value Supplier C9 10 µF, 100 V, Electrolytic, ±20% Panasonic C10* 0.1 µF, X7R, ±20% Murata, Johanson, Novacap, Venkel C14* 0.
PAGE 25
Si3216 Table 16. Si321xM MOSFET/Transformer DC-DC Converter Component Values Component (s) Value Supplier C9 10 µF, 100 V, Electrolytic, ±20% Panasonic C14* 0.
PAGE 26
Si3216 Table 17. Si321x Optional Bias Component Values Component Value Supplier/Part Number C7,C8 100 nF, 100 V, X7R, 20% Murata, Johanson, Venkel R23,R24 3.0 k, 1/10 W, 5% The subcircuit above can be substituted into any of the ProSLIC solutions as an optional bias circuit for Q5, Q6. For this optional subcircuit, C7 and C8 are different in voltage and capacitance to the standard circuit. R23 and R24 are additional components. N ot fo R r N ec e w om m D e e s nd ig e ns d Table 18.
PAGE 27
Si3216 2. Functional Description 2.1.1. DC Feed Characteristics The ProSLIC has programmable constant voltage and constant current zones as depicted in Figure 16. Open circuit TIP-to-RING voltage (VOC) defines the constant voltage zone and is programmable from 0 V to 94.5 V in 1.5 V steps. The loop current limit (ILIM) defines the constant current zone and is programmable from 20 mA to 41 mA in 3 mA steps. The ProSLIC has an inherent dc output resistance (RO) of 160 .
PAGE 28
Si3216 2.1.2. Linefeed Architecture The ProSLIC is a low-voltage CMOS device that uses either an Si3201 linefeed interface IC or low-cost external components to control the high voltages required for subscriber line interfaces. Figure 17 is a simplified illustration of the linefeed control loop circuit for TIP or RING and the external components used. N ot fo R r N ec e w om m D e e s nd ig e ns d The ProSLIC uses both voltage and current sensing to control TIP and RING.
PAGE 29
Si3216 Audio Codec M onitor A/D A/D A/D DSP D/A D/A SLIC DAC  DC Control N ot fo R r N ec e w om m D e e s nd ig e ns d External Com ponents On-Chip Battery Sense AC Control AC Sense Em itter Sense DC Sense R AC C AC AC Control Loop QP Q DN R BP TIP or RING DC Control Loop R DC R SE R BAT QN RE V BAT Figure 17. Simplified ProSLIC Linefeed Architecture for TIP and RING Leads (One Shown) Table 22.
PAGE 30
Si3216 Table 23. Measured Real Time Linefeed Interface Characteristics Measurement Range Resolution Register Bits Location* Loop Voltage Sense (VTIP – VRING) –94.5 to +94.5 V 1.5 V LVSP, LVS[6:0] Direct Register 78 Loop Current Sense –80 to +80 mA 1.27 mA LCSP, LCS[5:0] Direct Register 79 TIP Voltage Sense 0 to –95.88 V 0.376 V VTIP[7:0] Direct Register 80 N ot fo R r N ec e w om m D e e s nd ig e ns d Parameter RING Voltage Sense 0 to –95.88 V 0.
PAGE 31
Si3216 Table 24. Associated Power Monitoring and Power Fault Registers Description/ Range Resolution Power Monitor Pointer 0 to 5 points to Q1 to Q6, respectively N/A 30.4 mW Line Power Monitor Output 0 to 7.8 W for Q1, Q2, Q5, Q6 0 to 0.9 W for Q3, Q4 Power Alarm Threshold, Q1 & Q2 0 to 7.8 W 30.4 mW PPT12[7:0] Indirect Register 19 Power Alarm Threshold, Q3 & Q4 0 to 0.9 W 3.62 mW PPT34[7:0] Indirect Register 20 Power Alarm Threshold, Q5 & Q6 0 to 7.8 W 30.
PAGE 32
Si3216 LCS LVS Input Signal Processor ISP_OUT Digital LPF + Debounce Filter LCR Interrupt Logic LCIP – NCLR LCDI LFS LCVE LCIE Loop Closure Threshold N ot fo R r N ec e w om m D e e s nd ig e ns d HYSTEN LCRT LCRTL Figure 18. Loop Closure Detection 2.1.6. Loop Closure Detection 2.1.8. Voltage-Based Loop Closure Detection A loop closure event signals that the terminal equipment has gone off-hook during On-Hook Transmission or OnHook Active states.
PAGE 33
Si3216 2.1.9. Linefeed Calibration An internal calibration algorithm corrects for internal and external component errors. The calibration is initiated by setting the CAL bit in direct Register 96. Upon completion of the calibration cycle, this bit is automatically reset. Table 26. Si321x and Si321xM Differences Device DCFF Signal Polarity Si321x = DCDRV = DCDRV Si321xM DCPOL 0 1 Notes: 1. DCFF signal polarity with respect to DCDRV signal. 2. Direct Register 93, bit 5; This is a read-only bit.
PAGE 34
Si3216 power supply (number of REN supported). Because the ProSLIC dynamically regulates its own battery supply voltage using the dc-dc converter controller, the battery voltage (VBAT) is offset from the negative-most terminal by a programmable voltage (VOV) to allow voltage headroom for carrying audio signals. As mentioned previously, the ProSLIC dynamically adjusts VBAT to suit the particular circuit requirement. To illustrate this, the behavior of VBAT in the Active state is shown in Figure 19.
PAGE 35
Si3216 VOC ILIM Constant I Region Constant V Region RLOOP VCM VTIP VBATL CK =1 VOC |VTIP - VRING| N ot fo R r N ec e w om m D e e s nd ig e ns d TR A TRACK=0 VOV VRING VOV V VBAT Figure 19. VTIP, VRING, and VBAT in the Forward Active State Table 27.
PAGE 36
Si3216 2.2.5. DC-DC Converter Enhancements described above. The ProSLIC supports two selectable enhancements to the dc-dc converter. The first is a multi-threshold error control algorithm that enables the dc-dc converter to adjust more quickly to voltage changes. This option is enabled by setting DCSU = 1 (direct Register 108, bit 5). The second enhancement is an audio band filter that removes audio band noise from the dc-dc converter control loop.
PAGE 37
Si3216 2.3.2. Oscillator Frequency and Amplitude 2.3.3. Tone Generator Cadence Programming Each of the two-tone generators contains a two-pole resonant oscillator circuit with a programmable frequency and amplitude. These two-tone generators are programmed via indirect registers OSC1, OSC1X, OSC1Y, OSC2, OSC2X, and OSC2Y. The sample rate for the two oscillators is 16 kHz.
PAGE 38
Si3216 Table 28.
PAGE 39
Si3216 2.3.4. Enhanced FSK Waveform Generation 2.4.1. Ringing Architecture Enhanced FSK generation capabilities can be enabled by setting FSKEN = 1 (direct Register 108, bit 6) and REN = 1 (direct Register 32, bit 6). In this mode, the user can define mark (1) and space (0) attributes once during initialization by defining indirect Registers 69–74. The user need only indicate 0-to-1 and 1-to-0 transitions in the information stream.
PAGE 40
Si3216 Table 29.
PAGE 41
Si3216 In addition, the user must select the trapezoidal ringing waveform by writing TSWS = 1 in direct Register 34. VTIP-RING 2.4.4. Ringing DC Voltage Offset A dc offset can be added to the ac ringing waveform by defining the offset voltage in ROFF (indirect Register 6). The offset, VROFF, is added to the ringing signal when RVO is set to 1 (direct Register 34, bit 1). The value of ROFF is calculated as follows: VROFF T=1/freq time 2.4.5.
PAGE 42
Si3216 V BATH = V AC,PK + V ROFF + V OVR The ProSLIC is designed to create a fully-balanced ringing waveform, meaning that the TIP and RING common mode voltage, (VTIP + VRING)/2, is fixed. This voltage is referred to as VCM_RING and is automatically set to the following: V BATH – V CMR V CM_RING = -------------------------------------2 The ProSLIC has a mode to briefly increase the maximum differential current limit between the voltage transition of TIP and RING from ringing to a dc linefeed state.
PAGE 43
Si3216 Table 30.
PAGE 44
TIP RING 44 Ibuf Off Chip Gm On Chip RAC XAC – + THPF ADCG ARX D/A ALM1 Interpolation Filter DLM Digital Loopback RHPF DACG Dual Tone Generator Figure 24. AC Signal Path Block Diagram HYBA H Analog Loopback A/D Decimation Filter + Mute + RXM Mute TXM u/A-law Compressor u/A-law Expander N ot fo R r N ec e w om m D e e s nd ig e ns d +– ATX Transmit Path ALM2 Serial Input Full Analog Loopback Serial Output Digital RX Digital TX Si3216 Rev. 1.
PAGE 45
Si3216 2.5.2. Receive Path 2.5.5. Loopback Testing In the receive path, digital voice is expanded from µ/Alaw if enabled. DACG is the receive path programmable gain amplifier which can be programmed from – dB to 6 dB. A 16-bit signal is then provided to a D/A converter. The resulting analog signal is amplified by the analog receive amplifier, ARX, which has the following gain options: mute, –3.5, 0, and 3.5 dB.
PAGE 46
Si3216 subscriber loop via the ITIPP and IRINGP pins through an off-chip current buffer (IBUF), which is implemented using transistors Q1 and Q2 (see Figure on page 22). Gm is referenced to an off-chip resistor (R15). The ProSLIC also provides a means of compensating for degraded subscriber loop conditions involving excessive line capacitance (leakage). The CLC[1:0] bits of direct Register 10 increase the ac signal magnitude to compensate for the additional loss at the high end of the audio frequency range.
PAGE 47
Si3216 There are a number of variations of usage on this fourwire interface:  Continuous clocking. During continuous clocking, the data transfers are controlled by the assertion of the CS pin. CS must assert before the falling edge of SCLK on which the first bit of data is expected during a read cycle and must remain low for the duration of Don't Care SCLK CS the 8 bit transfer (command/address or data).  SDI/SDO wired operation.
PAGE 48
Si3216 SDO CPU CS SDI0 SDI CS SDO SDI SDITHRU SDI1 SDI N ot fo R r N ec e w om m D e e s nd ig e ns d CS SDO SDITHRU SDI2 SDI CS SDO SDITHRU SDI3 SDI CS SDO SDITHRU Chip Select Byte SCLK Address Byte Data Byte SDI0 C7 C6 C5 C4 C3 C2 C1 C0 R/W A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 SDI1 – C7 C6 C5 C4 C3 C2 C1 R/W A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 SDI2 – – C7 C6 C5 C4 C3 C2 R/W A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 SDI3 – – – C7 C6 C5 C4 C3 R
PAGE 49
Si3216 2.10. PCM Interface Figure 29 illustrates the use of the PCM in wideband mode. DTX data is high-impedance except for the duration of the 16-bit PCM transmit. DTX returns to high-impedance either on the negative edge of PCLK during the LSB or on the positive edge of PCLK following the LSB. This is based on the setting of the TRI bit of the PCM Mode Select register.
PAGE 50
Si3216 Table 32. µ-Law Encode-Decode Characteristics1,2 8 7 6 5 4 3 2 #Intervals X Interval Size 16 X 256 Value at Segment Endpoints Digital Code Decode Level 8159 . . . 4319 4063 10000000b 8031 10001111b 4191 N ot fo R r N ec e w om m D e e s nd ig e ns d Segment Number 16 X 128 16 X 64 16 X 32 16 X 16 16 X 8 16 X 4 15 X 2 1 __________________ 1 X 1 . . . 2143 2015 10011111b 2079 . . . 1055 991 10101111b 1023 . . . 511 479 10111111b 495 . . . 239 223 11001111b 231 . .
PAGE 51
Si3216 Table 33. A-Law Encode-Decode Characteristics1,2 7 6 5 4 3 2 1 #intervals X interval size 16 X 128 Value at segment endpoints 4096 3968 . . 2176 2048 Digital Code Decode Level 10101010b 4032 10100101b 2112 N ot fo R r N ec e w om m D e e s nd ig e ns d Segment Number 16 X 64 16 X 32 16 X 16 16 X 8 16 X 4 32 X 2 . . . 1088 1024 10110101b 1056 . . . 544 512 10000101b 528 . . . 272 256 10010101b 264 . . . 136 128 11100101b 132 . . . 68 64 11110101b 66 . . .
PAGE 52
Si3216 3. Control Registers Note: Any register not listed here is reserved and must not be written. Table 34.
PAGE 53
Si3216 Table 34.
PAGE 54
Si3216 Table 34.
PAGE 55
Si3216 Table 34.
PAGE 56
Si3216 Register 0. SPI Mode Select Bit D7 D6 D5 D4 D3 D2 D1 Name SPIDC SPIM PNI[1:0] RNI[3:0] Type R/W R/W R R Reset settings = 00xx_xxxx Name 7 SPIDC 6 SPIM 5:4 PNI[1:0] Function N ot fo R r N ec e w om m D e e s nd ig e ns d Bit SPI Daisy Chain Mode Enable. 0 = Disable SPI daisy chain mode. 1 = Enable SPI daisy chain mode. SPI Mode. 0 = Causes SDO to tri-state on rising edge of SCLK of LSB. 1 = Normal operation; SDO tri-states on rising edge of CS. Part Number Identification.
PAGE 57
Si3216 Register 1. PCM Mode Select Bit D7 D6 D5 Name PNI2 WBE PCME Type R R/W R/W D4 D3 D2 D1 D0 PCMF[1:0] PCMT GCI TRI R/W R/W R/W R/W Reset settings = 1000_1000 Name 7 PNI2 Function N ot fo R r N ec e w om m D e e s nd ig e ns d Bit Part Number Identification 2. Note: PNI[2:0] can be read in direct Register 6. 0 = Si3210, Si3211 family. 1 = Si3216 family. 6 WBE 5 PCME 4:3 PCMF[1:0] 2 PCMT 1 GCI GCI Clock Format. 0 = 1 PCLK per data bit. 1 = 2 PCLKs per data bit.
PAGE 58
Si3216 Register 2. PCM Transmit Start Count—Low Byte Bit D7 D6 D5 D4 D3 Name TXS[7:0] Type R/W D2 D1 D0 Reset settings = 0000_0000 Name 7:0 TXS[7:0] Function N ot fo R r N ec e w om m D e e s nd ig e ns d Bit PCM Transmit Start Count. PCM transmit start count equals the number of PCLKs following FSYNC before data transmission begins. See Figure 29 on page 49. Register 3.
PAGE 59
Si3216 Register 5. PCM Receive Start Count—High Byte Bit D7 D6 D5 D4 D3 D2 D1 D0 Name RXS[9:8] Type R/W Reset settings = 0000_0000 Name Function 7:2 Reserved Read returns zero. 1:0 RXS[9:8] PCM Receive Start Count. PCM receive start count equals the number of PCLKs following FSYNC before data reception begins. See Figure 29 on page 49. N ot fo R r N ec e w om m D e e s nd ig e ns d Bit Register 6.
PAGE 60
Si3216 Register 8. Audio Path Loopback Control Bit D7 D6 D5 D4 D3 D2 D1 D0 Name ALM2 DLM ALM1 Type R/W R/W R/W Reset settings = 0000_0010 Name 7:3 Reserved 2 ALM2 Analog Loopback Mode 2. (See Figure 24 on page 44.) 0 = Full analog loopback mode disabled. 1 = Full analog loopback mode enabled. 1 DLM Digital Loopback Mode. (See Figure 24 on page 44.) 0 = Digital loopback disabled. 1 = Digital loopback enabled. 0 ALM1 Analog Loopback Mode 1. (See Figure 24 on page 44.
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Si3216 Register 9. Audio Gain Control Bit D7 D6 D5 D4 D3 D2 D1 D0 Name RXHP TXHP TXM RXM ATX[1:0] ARX[1:0] Type R/W R/W R/W R/W R/W R/W Reset settings = 0000_0000 Name Function 7 RXHP Receive Path High Pass Filter Disable. 0 = HPF enabled in receive path, RHDF. 1 = HPF bypassed in receive path, RHDF. 6 TXHP Transmit Path High Pass Filter Disable. 0 = HPF enabled in transmit path, THPF. 1 = HPF bypassed in transmit path, THPF. 5 TXM Transmit Path Mute.
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Si3216 Register 10. Two-Wire Impedance Synthesis Control Bit D7 D6 D5 D4 D3 D2 D1 Name CLC[1:0] TISE TISS[2:0] Type R/W R/W R/W D0 Reset settings = 0000_1000 Name 7:6 Reserved Read returns zero. 5:4 CLC[1:0] Line Capacitance Compensation. 00 = Off 01 = 4.7 nF 10 = 10 nF 11 = Reserved 3 TISE 2:0 TISS[2:0] 62 Function N ot fo R r N ec e w om m D e e s nd ig e ns d Bit Two-Wire Impedance Synthesis Enable. 0 = Two-wire impedance synthesis disabled.
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Si3216 Register 11. Hybrid Control Bit D7 D6 D5 D4 D3 D2 D1 Name HYBP[2:0] HYBA[2:0] Type R/W R/W D0 Reset settings = 0011_0011 Name Function 7 Reserved Read returns zero. 6:4 HYBP[2:0] Pulse Metering Hybrid Adjustment. 000 = 4.08 dB 001 = 2.5 dB 010 = 1.16 dB 011 = 0 dB 100 = –1.02 dB 101 = –1.94 dB 110 = –2.77 dB 111 = Off 3 Reserved Read returns zero. 2:0 HYBA[2:0] Audio Hybrid Adjustment. 000 = 4.08 dB 001 = 2.5 dB 010 = 1.16 dB 011 = 0 dB 100 = –1.02 dB 101 = –1.
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Si3216 Register 14. Powerdown Control 1 Bit D7 D6 D5 D4 D3 Name DCOF Type R/W D2 D1 D0 PFR BIASOF SLICOF R/W R/W R/W Reset settings = 0001_0000 Name 7:5 Reserved 4 DCOF 3 PFR 2 Reserved 1 BIASOF DC Bias Power-Off Control. 0 = Automatic power control. 1 = Override automatic control and force dc bias circuitry off. 0 SLICOF SLIC Power-Off Control. 0 = Automatic power control. 1 = Override automatic control and force SLIC circuitry off.
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Si3216 Register 15. Powerdown Control 2 Bit D7 D6 D5 D4 D3 D2 D1 D0 Name ADCM ADCON DACM DACON GMM GMON Type R/W R/W R/W R/W R/W R/W Reset settings = 0000_0000 Name 7:6 Reserved 5 ADCM 4 ADCON 3 DACM 2 DACON 1 GMM 0 GMON Function N ot fo R r N ec e w om m D e e s nd ig e ns d Bit Read returns zero. Analog to Digital Converter Manual/Automatic Power Control. 0 = Automatic power control. 1 = Manual power control; ADCON controls on/off state.
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Si3216 Register 18. Interrupt Status 1 Bit D7 D6 D5 D4 D3 D2 D1 D0 Name RGIP RGAP O2IP O2AP O1IP O1AP Type R/W R/W R/W R/W R/W R/W Reset settings = 0000_0000 Name 7:6 Reserved 5 RGIP Ringing Inactive Timer Interrupt Pending. Writing 1 to this bit clears a pending interrupt. 0 = No interrupt pending. 1 = Interrupt pending. 4 RGAP Ringing Active Timer Interrupt Pending. Writing 1 to this bit clears a pending interrupt. 0 = No interrupt pending. 1 = Interrupt pending.
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Si3216 Register 19. Interrupt Status 2 Bit D7 D6 D5 D4 D3 D2 D1 D0 Name Q6AP Q5AP Q4AP Q3AP Q2AP Q1AP LCIP RTIP Type R/W R/W R/W R/W R/W R/W R/W R/W Reset settings = 0000_0000 Name Function 7 Q6AP Power Alarm Q6 Interrupt Pending. Writing 1 to this bit clears a pending interrupt. 0 = No interrupt pending. 1 = Interrupt pending. 6 Q5AP Power Alarm Q5 Interrupt Pending. Writing 1 to this bit clears a pending interrupt. 0 = No interrupt pending. 1 = Interrupt pending.
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Si3216 Register 20. Interrupt Status 3 Bit D7 D6 D5 D4 D3 D2 D1 Name INDP Type R/W D0 Reset settings = 0000_0000 Name 7:2 Reserved 1 INDP 0 Reserved 68 Function N ot fo R r N ec e w om m D e e s nd ig e ns d Bit Read returns zero. Indirect Register Access Serviced Interrupt. This bit is set once a pending indirect register service request has been completed. Writing 1 to this bit clears a pending interrupt. 0 = No interrupt pending. 1 = Interrupt pending. Read returns zero. Rev.
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Si3216 Register 21. Interrupt Enable 1 Bit D7 D6 D5 D4 D3 D2 D1 D0 Name RGIE RGAE O2IE O2AE O1IE O1AE Type R/W R/W R/W R/W R/W R/W Reset settings = 0000_0000 Name Function 7:6 Reserved 5 RGIE Ringing Inactive Timer Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. 4 RGAE Ringing Active Timer Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. 3 O2IE Oscillator 2 Inactive Timer Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled.
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Si3216 Register 22. Interrupt Enable 2 Bit D7 D6 D5 D4 D3 D2 D1 D0 Name Q6AE Q5AE Q4AE Q3AE Q2AE Q1AE LCIE RTIE Type R/W R/W R/W R/W R/W R/W R/W R/W Reset settings = 0000_0000 Name 7 Q6AE Power Alarm Q6 Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. 6 Q5AE Power Alarm Q5 Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. 5 Q4AE Power Alarm Q4 Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled.
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Si3216 Register 23. Interrupt Enable 3 Bit D7 D6 D5 D4 D3 D2 D1 Name INDE Type R/W D0 Reset settings = 0000_0000 Name 7:2 Reserved 1 INDE 0 Reserved Function N ot fo R r N ec e w om m D e e s nd ig e ns d Bit Read returns zero. Indirect Register Access Serviced Interrupt Enable. 0 = Interrupt masked. 1 = Interrupt enabled. Read/write bit with no function. Rev. 1.
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Si3216 Register 28. Indirect Data Access—Low Byte Bit D7 D6 D5 D4 D3 Name IDA[7:0] Type R/W D2 D1 D0 Reset settings = 0000_0000 Name 7:0 IDA[7:0] Function N ot fo R r N ec e w om m D e e s nd ig e ns d Bit Indirect Data Access—Low Byte. A write to IDA followed by a write to IAA will place the contents of IDA into an indirect register at the location referenced by IAA at the next indirect register update (16 kHz update rate—a write operation).
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Si3216 Register 30. Indirect Address Bit D7 D6 D5 D4 D3 Name IAA[7:0] Type R/W D2 D1 D0 Reset settings = xxxx_xxxx Name 7:0 IAA[7:0] Function N ot fo R r N ec e w om m D e e s nd ig e ns d Bit Indirect Address Access. A write to IDA followed by a write to IAA will place the contents of IDA into an indirect register at the location referenced by IAA at the next indirect register update (16 kHz update rate—a write operation).
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Si3216 Register 32. Oscillator 1 Control Bit D7 D6 D5 D4 D3 D2 D1 D0 Name OSS1 REL OZ1 O1TAE O1TIE O1E O1SO[1:0] Type R R/W R/W R/W R/W R/W R/W Reset settings = 0000_0000 Name 7 OSS1 6 REL Oscillator 1 Automatic Register Reload. This bit should be set for FSK signaling. 0 = Oscillator 1 will stop signaling after inactive timer expires. 1 = Oscillator 1 will continue to read register parameters and output signals. 5 OZ1 Oscillator 1 Zero Cross Enable.
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Si3216 Register 33. Oscillator 2 Control Bit D7 Name Type D6 D5 D4 D3 D2 D1 D0 OSS2 OZ2 O2TAE O2TIE O2E O2SO[1:0] R R/W R/W R/W R/W R/W Reset settings = 0000_0000 Name Function 7 OSS2 6 Reserved 5 OZ2 4 O2TAE Oscillator 2 Active Timer Enable. 0 = Disable timer. 1 = Enable timer. 3 O2TIE Oscillator 2 Inactive Timer Enable. 0 = Disable timer. 1 = Enable timer. 2 O2E 1:0 O2SO[1:0] N ot fo R r N ec e w om m D e e s nd ig e ns d Bit Oscillator 2 Signal Status.
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Si3216 Register 34. Ringing Oscillator Control Bit D7 Name Type D6 D5 D4 D3 D2 D1 D0 RSS RDAC RTAE RTIE ROE RVO TSWS R R R/W R/W R R/W R/W Reset settings = 0000_0000 Name 7 RSS 6 Reserved 5 RDAC Ringing Signal DAC/Linefeed Cross Indicator. For ringing signal start and stop, output to TIP and RING is suspended to ensure continuity with dc linefeed voltages. RDAC indicates that ringing signal is actually present at TIP and RING. 0 = Ringing signal not present at TIP and RING.
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Si3216 Register 36. Oscillator 1 Active Timer—Low Byte Bit D7 D6 D5 D4 D3 Name OAT1[7:0] Type R/W D2 D1 D0 Reset settings = 0000_0000 Name 7:0 OAT1[7:0] Function N ot fo R r N ec e w om m D e e s nd ig e ns d Bit Oscillator 1 Active Timer. LSB = 125 µs Register 37. Oscillator 1 Active Timer—High Byte Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0 D1 D0 OAT1[15:8] R/W Reset settings = 0000_0000 Bit Name 7:0 OAT1[15:8] Function Oscillator 1 Active Timer. Register 38.
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Si3216 Register 39. Oscillator 1 Inactive Timer—High Byte Bit D7 D6 D5 D4 D3 Name OIT1[15:8] Type R/W D2 D1 D0 Reset settings = 0000_0000 Name 7:0 OIT1[15:8] Function N ot fo R r N ec e w om m D e e s nd ig e ns d Bit Oscillator 1 Inactive Timer. Register 40. Oscillator 2 Active Timer—Low Byte Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0 D1 D0 OAT2[7:0] R/W Reset settings = 0000_0000 Bit Name 7:0 OAT2[7:0] Function Oscillator 2 Active Timer. LSB = 125 µs Register 41.
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Si3216 Register 42. Oscillator 2 Inactive Timer—Low Byte Bit D7 D6 D5 D4 D3 Name OIT2[7:0] Type R/W D2 D1 D0 Reset settings = 0000_0000 Name 7:0 OIT2[7:0] Function N ot fo R r N ec e w om m D e e s nd ig e ns d Bit Oscillator 2 Inactive Timer. LSB = 125 µs Register 43. Oscillator 2 Inactive Timer—High Byte Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0 D1 D0 OIT2[15:8] R/W Reset settings = 0000_0000 Bit Name 7:0 OIT2[15:8] Function Oscillator 2 Inactive Timer. Register 48.
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Si3216 Register 49. Ringing Oscillator Active Timer—High Byte Bit D7 D6 D5 D4 D3 Name RAT[15:8] Type R/W D2 D1 D0 Reset settings = 0000_0000 Name 7:0 RAT[15:8] Function N ot fo R r N ec e w om m D e e s nd ig e ns d Bit Ringing Active Timer. Register 50. Ringing Oscillator Inactive Timer—Low Byte Bit Name Type D7 D6 D5 D4 D3 D2 D1 D0 D1 D0 RIT[7:0] R/W Reset settings = 0000_0000 Bit Name 7:0 RIT[7:0] Function Ringing Inactive Timer. LSB = 125 µs Register 51.
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Si3216 Register 52. FSK Data Bit D7 D6 D5 D4 D3 D2 D1 D0 Name FSKDAT Type R/W Reset settings = 0000_0000 Name Function 7:1 Reserved Read returns zero. 0 FSKDAT FSK Data. When FSKEN = 1 (direct Register 108, bit 6) and REL = 1 (direct Register 32, bit 6), this bit serves as the buffered input for FSK generation bit stream data. N ot fo R r N ec e w om m D e e s nd ig e ns d Bit Register 63.
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Si3216 Register 64. Linefeed Control Bit D7 D6 D5 D4 D3 D2 D1 Name LFS[2:0] LF[2:0] Type R R/W D0 Reset settings = 0000_0000 Name 7 Reserved Read returns zero. 6:4 LFS[2:0] Linefeed Shadow. This register reflects the actual real time linefeed state. Automatic operations may cause actual linefeed state to deviate from the state defined by linefeed register (e.g.
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Si3216 Register 65. External Bipolar Transistor Control Bit D7 D6 D5 D4 D3 D2 D1 D0 Name SQH CBY ETBE ETBO[1:0] ETBA[1:0] Type R/W R/W R/W R/W R/W Reset settings = 0110_0001 Name Function 7 Reserved 6 SQH Audio Squelch. 0 = No squelch. 1 = STIPAC and SRINGAC pins squelched. 5 CBY Capacitor Bypass. 0 = Capacitors CP (C1) and CM (C2) in circuit. 1 = Capacitors CP (C1) and CM (C2) bypassed. 4 ETBE External Transistor Bias Enable. 0 = Bias disabled. 1 = Bias enabled.
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Si3216 Register 66. Battery Feed Control Bit D7 D6 D5 D4 D3 D2 D1 D0 Name VOV FVBAT TRACK Type R/W R/W R/W Reset settings = 0000_0011 Name 7:5 Reserved 4 VOV 3 FVBAT Function N ot fo R r N ec e w om m D e e s nd ig e ns d Bit Read returns zero. Overhead Voltage Range Increase. (See Figure 19 on page 35.) This bit selects the programmable range for VOV, which is defined in indirect Register 41. 0 = VOV = 0 V to 9 V 1 = VOV = 0 V to 13.5 V VBAT Manual Setting.
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Si3216 Register 67. Automatic/Manual Control Bit D7 D6 D5 D4 Name MNCM MNDIF Type R/W R/W D3 D2 D1 D0 SPDS AORD AOLD AOPN R/W R/W R/W R/W Reset settings = 0001_1111 Name Function 7 Reserved 6 MNCM Common Mode Manual/Automatic Select. 0 = Automatic control. 1 = Manual control, in which TIP (forward) or RING (reverse) forces voltage to follow VCM value. 5 MNDIF Differential Mode Manual/Automatic Select. 0 = Automatic control.
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Si3216 Register 68. Loop Closure/Ring Trip Detect Status Bit D7 D6 D5 D4 D3 D2 D1 D0 Name DBIRAW RTP LCR Type R R R Reset settings = 0000_0000 Name Function 7:3 Reserved Read returns zero. 2 DBIRAW Ring Trip/Loop Closure Unfiltered Output. The state of this bit reflects the real time output of ring trip and loop closure detect circuits before debouncing. 0 = Ring trip/loop closure threshold exceeded. 1 = Ring trip/loop closure threshold not exceeded.
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Si3216 Register 70. Ring Trip Detect Debounce Interval Bit D7 D6 D5 D4 D3 D2 Name RTDI[6:0] Type R/W D1 D0 Reset settings = 0000_1010 Name Function 7 Reserved Read returns zero. 6:0 RTDI[6:0] Ring Trip Detect Debounce Interval. The value written to this register defines the minimum steady state debounce time. The value may be set between 0 ms (0x00) to 159 ms (0x7F) in 1.25 ms steps. Default value = 12.5 ms. N ot fo R r N ec e w om m D e e s nd ig e ns d Bit Register 71.
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Si3216 Register 72. On-Hook Line Voltage Bit D7 D6 D5 D4 D3 D2 Name VSGN VOC[5:0] Type R/W R/W D1 D0 Reset settings = 0010_0000 Name 7 Reserved 6 VSGN 5:0 VOC[5:0] Function N ot fo R r N ec e w om m D e e s nd ig e ns d Bit Read returns zero. On-Hook Line Voltage. The value written to this bit sets the on-hook line voltage polarity (VTIP–VRING). 0 = VTIP–VRINGis positive. 1 = VTIP–VRING is negative. On-Hook Line Voltage.
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Si3216 Register 74. High Battery Voltage Bit D7 D6 D5 D4 D3 D2 Name VBATH[5:0] Type R/W D1 D0 Reset settings = 0011_0010 Name 7:6 Reserved 5:0 VBATH[5:0] Function N ot fo R r N ec e w om m D e e s nd ig e ns d Bit Read returns zero. High Battery Voltage. The value written to this register sets high battery voltage. VBATH must be greater than or equal to VBATL. The value may be set between 0 V (0x00) and –94.5 V (0x3F) in 1.5 V steps. Default value = –75 V. Register 75.
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Si3216 Register 76. Power Monitor Pointer Bit D7 D6 D5 D4 D3 D2 D1 Name PWRMP[2:0] Type R/W D0 Reset settings = 0000_0000 Name 7:3 Reserved 2:0 PWRMP[2:0] Function N ot fo R r N ec e w om m D e e s nd ig e ns d Bit Read returns zero. Power Monitor Pointer. Selects the external transistor from which to read power output. The power of the selected transistor is read in the PWROM register. 000 = Q1 001 = Q2 010 = Q3 011 = Q4 100 = Q5 101 = Q6 110 = Undefined 111 = Undefined Register 77.
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Si3216 Register 78. Loop Voltage Sense Bit D7 D6 D5 D4 D3 D2 Name LVSP LVS[5:0] Type R R D1 D0 Reset settings = 0000_0000 Name 7 Reserved 6 LVSP 5:0 LVS[5:0] Function N ot fo R r N ec e w om m D e e s nd ig e ns d Bit Read returns zero. Loop Voltage Sense Polarity. This register reports the polarity of the differential loop voltage (VTIP – VRING). 0 = Positive loop voltage (VTIP > VRING). 1 = Negative loop voltage (VTIP < VRING). Loop Voltage Sense Magnitude.
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Si3216 Register 80. TIP Voltage Sense Bit D7 D6 D5 D4 D3 Name VTIP[7:0] Type R D2 D1 D0 Reset settings = 0000_0000 Name 7:0 VTIP[7:0] Function N ot fo R r N ec e w om m D e e s nd ig e ns d Bit TIP Voltage Sense. This register reports the real time voltage at TIP with respect to ground. The range is 0 V (0x00) to –95.88 V (0xFF) in. 376 V steps. Register 81.
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Si3216 Register 83. Battery Voltage Sense 2 Bit D7 D6 D5 D4 D3 Name VBATS2[7:0] Type R D2 D1 D0 Reset settings = 0000_0000 Name 7:0 VBATS2[7:0] Function N ot fo R r N ec e w om m D e e s nd ig e ns d Bit Battery Voltage Sense 2. This register is one of two registers that reports the real time voltage at VBAT with respect to ground. The range is 0 V (0x00) to –95.88 V (0xFF) in .376 V steps. Register 84.
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Si3216 Register 86. Transistor 3 Current Sense Bit D7 D6 D5 D4 D3 Name IQ3[7:0] Type R D2 D1 D0 Reset settings = xxxx_xxxx Name 7:0 IQ3[7:0] Function N ot fo R r N ec e w om m D e e s nd ig e ns d Bit Transistor 3 Current Sense. This register reports the real time current through Q3. The range is 0 A (0x00) to 9.59 mA (0xFF) in 37.6 µA steps. Register 87.
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Si3216 Register 89. Transistor 6 Current Sense Bit D7 D6 D5 D4 D3 Name IQ6[7:0] Type R D2 D1 D0 Reset settings = xxxx_xxxx Name 7:0 IQ6[7:0] Function N ot fo R r N ec e w om m D e e s nd ig e ns d Bit Transistor 6 Current Sense. This register reports the real time current through Q6. The range is 0 A (0x00) to 80.58 mA (0xFF) in .316 mA steps. Register 92.
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Si3216 Register 93. DC-DC Converter Switching Delay Bit D7 D6 D5 D4 D3 D2 Name DCCAL DCPOL DCTOF[4:0] Type R/W R R/W D1 D0 Reset settings = 0001_0100 (Si3216) N ot fo R r N ec e w om m D e e s nd ig e ns d Reset settings = 0011_0100 (Si3216M) Bit Name 7 DCCAL 6 Reserved 5 DCPOL 4:0 DCTOF[4:0] Function DC-DC Converter Peak Current Monitor Calibration Status. Writing a one to this bit starts the dc-dc converter peak current monitor calibration routine. 0 = Normal operation.
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Si3216 Register 96. Calibration Control/Status Register 1 Bit D7 D6 D5 D4 D3 D2 D1 D0 Name CAL CALSP CALR CALT CALD CALC CALIL Type R/W R/W R/W R/W R/W R/W R/W Reset settings = 0001_1111 Name Function 7 Reserved 6 CAL 5 CALSP 4 CALR RING Gain Mismatch Calibration. For use with discrete solution only. When using the Si3201, consult “AN35: Si321x User’s Quick Reference Guide” and follow the instructions for manual calibration. 0 = Normal operation or calibration complete.
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Si3216 Register 97. Calibration Control/Status Register 2 Bit D7 D6 D5 D4 D3 D2 D1 Name CALM1 CALM2 CALDAC CALADC Type R/W R/W R/W R/W Reset settings = 0001_1110 Name 7:5 Reserved 4 CALM1 Monitor ADC Calibration 1. 0 = Normal operation or calibration complete. 1 = Calibration enabled or in progress. 3 CALM2 Monitor ADC Calibration 2. 0 = Normal operation or calibration complete. 1 = Calibration enabled or in progress. 2 CALDAC DAC Calibration.
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Si3216 Register 98. RING Gain Mismatch Calibration Result Bit D7 D6 D5 D4 D3 D2 Name CALGMR[4:0] Type R/W D1 D0 Reset settings = 0001_0000 Name 7:5 Reserved 4:0 CALGMR[4:0] Function N ot fo R r N ec e w om m D e e s nd ig e ns d Bit Read returns zero. Gain Mismatch of IE Tracking Loop for RING Current. Register 99.
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Si3216 Register 101. Common Mode Loop Current Gain Calibration Result Bit D7 D6 D5 D4 D3 D2 D1 Name CALGC[4:0] Type R/W D0 Reset settings = 0001_0001 Name 7:5 Reserved 4:0 CALGC[4:0] Function N ot fo R r N ec e w om m D e e s nd ig e ns d Bit Read returns zero. Common Mode DAC Gain Calibration Result. Register 102.
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Si3216 Register 104. Analog DAC/ADC Offset Bit D7 D6 D5 D4 D3 D2 D1 D0 Name DACP DACN ADCP ADCN Type R/W R/W R/W R/W Reset settings = 0000_0000 Name Function 7:4 Reserved 3 DACP Positive Analog DAC Offset. 2 DACN Negative Analog DAC Offset. 1 ADCP Positive Analog ADC Offset. 0 ADCN Negative Analog ADC Offset. N ot fo R r N ec e w om m D e e s nd ig e ns d Bit Read returns zero. Register 105.
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Si3216 Register 108. Enhancement Enable Bit D7 D6 D5 Name ILIMEN FSKEN Type R/W R/W D4 D3 D2 D1 D0 DCSU LCVE DCFIL HYSTEN R/W R/W R/W R/W Reset settings = 0000_0000 Name 7 ILIMEN Current Limit Increase. When enabled, this bit temporarily increases the maximum differential current limit at the end of a ring burst to enable a faster settling time to a dc linefeed state. 0 = The value programmed in ILIM (direct Register 71) is used.
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Si3216 Name Function 1 DCFIL DC-DC Converter Squelch. When enabled, this bit squelches noise in the audio band from the dc-dc converter control loop. 0 = Voice band squelch disabled. 1 = Voice band squelch enabled. 0 HYSTEN Loop Closure Hysteresis Enable. When enabled, this bit allows hysteresis to the loop closure calculation. The upper and lower hysteresis thresholds are defined by Indirect Registers 28 and 43, respectively. 0 = Loop closure hysteresis disabled. 1 = Loop closure hysteresis enabled.
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Si3216 4. Indirect Registers Indirect registers are not directly mapped into memory but are accessible through the IDA and IAA registers. A write to IDA followed by a write to IAA is interpreted as a write request to an indirect register. In this case, the contents of IDA are written to indirect memory at the location referenced by IAA at the next indirect register update. A write to IAA without first writing to IDA is interpreted as a read request from an indirect register.
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Si3216 Table 36. Oscillator Indirect Registers Summary (Continued) Addr. D15 D14 D13 D12 D11 D10 D9 D8 D7 7 RCO[15:0] 8 RNGX[15:0] 9 RNGY[15:0] D6 D5 D4 D3 D2 D1 D0 Table 37. Oscillator Indirect Registers Description Description Reference Page N ot fo R r N ec e w om m D e e s nd ig e ns d Addr. 0 Oscillator 1 Frequency Coefficient. Sets tone generator 1 frequency. 37 1 Oscillator 1 Amplitude Register. Sets tone generator 1 signal amplitude.
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Si3216 Table 39. Digital Programmable Gain/Attenuation Indirect Registers Description Description Reference Page 13 Receive Path Digital to Analog Converter Gain/Attenuation. This register sets gain/attenuation for the receive path. The digitized signal is effectively multiplied by DACG to achieve gain/attenuation. A value of 0x00 corresponds to – dB gain (mute). A value of 0x400 corresponds to unity gain. A value of 0x7FF corresponds to a gain of 6 dB.
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Si3216 4.3. SLIC Control See descriptions of linefeed interface and power monitoring for guidelines on computing register values. All values are represented in 2s-complement format. Note: The values of all indirect registers are undefined following the reset state. Shaded areas denote bits that can be read and written but should be written to zeroes. Table 40. SLIC Control Indirect Registers Summary Addr.
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Si3216 Table 41. SLIC Control Indirect Registers Description (Continued) Addr. Description Reference Page Power Alarm Threshold for Transistors Q1 and Q2. 30 20 Power Alarm Threshold for Transistors Q3 and Q4. 30 21 Power Alarm Threshold for Transistors Q5 and Q6. 30 22 Loop Closure Filter Coefficient. 32 23 Ring Trip Filter Coefficient. 42 24 Thermal Low Pass Filter Pole for Transistors Q1 and Q2. 30 25 Thermal Low Pass Filter Pole for Transistors Q3 and Q4.
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Si3216 4.4. FSK Control For detailed instructions on FSK signal generation, refer to “Application Note 32: FSK Generation” (AN32). These registers support enhanced FSK generation mode, which is enabled by setting FSKEN = 1 (direct Register 108, bit 6) and REL = 1 (direct Register 32, bit 6). Table 42. FSK Control Indirect Registers Summary Addr.
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Si3216 5.
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Si3216 Pin # QFN Pin # TSSOP Name 5 9 SDCL Description DC Monitor. DC-DC converter monitor input used to detect overcurrent situations in the converter. 6 10 VDDA1 Analog Supply Voltage. Analog power supply for internal analog circuitry. 7 11 IREF Current Reference. 8 N ot fo R r N ec e w om m D e e s nd ig e ns d Connects to an external resistor used to provide a high accuracy reference current. 12 CAPP SLIC Stabilization Capacitor.
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Si3216 Pin # QFN Pin # TSSOP Name 24 28 ITIPP Description Positive TIP Current Control. Analog current output driving Q1. 25 29 ITIPN Negative TIP Current Control. Analog current output driving Q4. 26 30 VDDD Digital Supply Voltage. Digital power supply for internal digital circuitry. 31 GNDD Digital Ground. N ot fo R r N ec e w om m D e e s nd ig e ns d 27 Ground connection for internal digital circuitry. 28 32 TEST Test. Enables test modes for Silicon Labs internal testing.
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Si3216 6. Pin Descriptions: Si3201 1 2, 6, 9, 12 3 4 5 7 8 10 1 16 ITIPP NC 2 15 RING 3 14 ITIPN IRINGP VBAT VBATH 4 13 IRINGN 5 12 NC NC 6 11 STIPE GND 7 10 SRINGE VDD 8 9 NC N ot fo R r N ec e w om m D e e s nd ig e ns d Pin # TIP Name Input/ Output TIP I/O TIP Output—Connect to the TIP lead of the subscriber loop. No Internal Connection—Do not connect to any electrical signal. NC RING Description I/O RING Output—Connect to the RING lead of the subscriber loop.
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Si3216 7. Ordering Guides Table 44.
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Si3216 Table 45.
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Si3216 8. Package Outline: 38-Pin QFN N ot fo R r N ec e w om m D e e s nd ig e ns d Figure 30 illustrates the package details for the Si321x. Table 46 lists the values for the dimensions shown in the illustration. Figure 30. 38-Pin Quad Flat No-Lead Package (QFN) Table 46. Package Diagram Dimensions1,2,3 Millimeters Symbol Min Nom Max A 0.75 0.85 0.95 A1 0.00 0.01 0.05 b 0.18 0.23 0.30 D D2 5.00 BSC. 3.10 3.20 e 0.50 BSC. E 7.00 BSC. 3.30 E2 5.10 5.20 5.30 L 0.35 0.
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Si3216 9. Package Outline: 38-Pin TSSOP Figure 31 illustrates the package details for the Si321x. Table 47 lists the values for the dimensions shown in the illustration. B 2x E/2 E1 N ot fo R r N ec e w om m D e e s nd ig e ns d E  L ddd C B A e 2x ccc A D aaa C A Seating Plane b A1 38x C bbb M C B A C Approximate device weight is 115.7 mg Figure 31. 38-Pin Thin Shrink Small Outline Package (TSSOP) Table 47. Package Diagram Dimensions Millimeters Symbol Min Nom Max A — — 1.
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Si3216 10. Package Outline: 16-Pin ESOIC Figure 32 illustrates the package details for the Si3201. Table 48 lists the values for the dimensions shown in the illustration. 16 9 h E H –B– x45° .25 M B M  1 8 L Bottom Side Exposed Pad 2.3 x 3.6 mm N ot fo R r N ec e w om m D e e s nd ig e ns d B .25 M C A M B S –A– Detail F D C A –C– e Seating Plane See Detail F A1  Weight: Approximate device weight is 0.15 grams. Figure 32.
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Si3216 11.
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Si3216 DOCUMENT CHANGE LIST Revision 0.61 to Revision 0.9  Separated the Si3216/15 document into two data sheets.  Added Quad Flat No-Lead (QFN) package.  Removed references to Si3215.  Updated Figure 11 on page 20. Changed Changed  C10 from 22 nF to 0.1 µF. Updated Table 11 on page 18. Changed 440 ns  delay time between chip selects, tcs, from 220 ns to Updated Table 41 on page 107. Changed recommended values for Indirect Register 27 from 6 to 0.  C18, C19 from 1.0 µF to 4.7 µF.
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N ot fo R r N ec e w om m D e e s nd ig e ns d Si3216 NOTES: Rev. 1.
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Si3216 CONTACT INFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 N ot fo R r N ec e w om m D e e s nd ig e ns d Email: ProSLICinfo@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
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