Data Sheet

20
FORM NO.: FR2-015_ A Responsible Department：WBU Expiry Date: Forever
The information contained herein is the exclusive property of AzureWave and shall not be distributed, reproduced, or
disclosed in whole or in part without prior written permission of AzureWave.
8
PCM_IN hold
8
ns
9
Delay from rising edge of
PCM_BCLK during last bit period to
PCM_OUT becoming high
impedance
0
25
ns
PCM Timing Diagram (Long Frame Sync, Master Mode)
Reference Characteristics
Minimum
Typical
Maximum
Unit
1
PCM bit clock frequency
12
MHz
2
PCM bit clock low
41
ns
3
PCM bit clock high
41
ns
4
PCM_SYNC delay
0
25
ns
5
PCM_OUT delay
0
25
ns
6
PCM_IN setup
8
ns
7
PCM_IN hold
8
ns
8
Delay from rising edge of
PCM_BCLK during last bit period to
PCM_OUT becoming high
impedance
0
25
ns