User's Manual

Values are specified in the recommended operating conditions unless otherwise specified.
Symbol Description Min Typ Max Units
1 PCM bit clock frequency 128 2048 kHz
2 PCM bit clock high time 209 ns
3 PCM bit clock low time 209 ns
4
Setup time for BT_PCM_SYNC before falling edge of BT_PCM_CLK
during first bit time
50 ns
5
Hold time for BT_PCM_SYNC after falling edge of BT_PCM_CLK during
second bit period. (BT_PCM_SYNC may go low any time from second
bit period to last bit period)
10 ns
6
Delay from rising edge of BT_PCM_CLK or BT_PCM_SYNC (whichever
is later) to data valid for first bit on BT_PCM_OUT
50 ns
7 Hold time of BT_PCM_OUT after BT_PCM_CLK falling edge 175 ns
8 Setup time for BT_PCM_IN before BT_PCM_CLK falling edge 50 ns
9 Hold time for BT_PCM_IN after BT_PCM_CLK falling edge 10
10
Delay from falling edge of BT_PCM_CLK or BT_PCM_SYNC (whichever
is later) during last bit in slot to BT_PCM_OUT becoming high
impedance
100 ns
2-5. SDIO Timing
The AW-NH930 has an internal power-on reset (POR) circuit. The device will be held in reset for a
maximum of 110 ms after VDDC and VDDIO have both passed the 0.6V threshold. Wait at least 110 ms
after VDD_CORE and VDDIO are available before initiating SDIO accesses. The external reset signals
are logically ORed with this POR. So if either the internal POR or one of the external resets is asserted,
the device will be in reset.
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