User's Manual

11
5.4 PCIe Bus during power on sequence
T
on
: The main power ramp up duration
T
PVPGL
: Power valid PERST# input inactive
T
PERST#-CLK
: Reference clock stable before PERST# inactive
T
attach
: USB attach state
T
k-state
: the duration from resister attached to USB host starting card detection procedure.
If use the 1.8V VIO, we suggest timing range 100us ~ 3ms after 3.3V power supply.
The typical timing range
Symbol Unit Min Typical Max
T
on
ms 1 1.5 5
T
PVPGL
ms --
T
PERST#-CLK
us 100 --
T
attach
ms 2 7 15
T
k-state
ms 50 250 --